am64x/am243: tamagawa: update documentation

- update documentation

Fixes: PINDSW-5472

Signed-off-by: Manoj Koppolu <manoj_koppolu@ti.com>

docs_src/docs/api_guide/components/position_sense/tamagawa_design.md

@@ -29,7 +29,8 @@ Refer PRU-ICSS chapter of AM64x/AM243x Technical Reference Manual
 At start-up, the application running on the ARM Cortex-R5 initializes the module clocks and configures the pinmux. The PRU is initialized and the PRU firmware is loaded on PRU slice of choice for a chosen ICSS instance (tested on PRU1 on ICSSG0). After the PRU1 starts executing, the Tamagawa interface is operational and the application can use it to communicate with an encoder. Use the Tamagawa diagnostic example to learn more about initialization and communication with the Tamagawa interface. This Tamagawa diagnostic example, also provides an easy way to validate the Tamagawa transactions. The diagnostic example provides menu options on the host PC in a serial terminal application, where the user can select the data ID code to be sent. Based on the data ID code, the application updates the Tamagwa interface with the data ID code and trigger transaction. The application then waits until it receives an indication of complete transaction by the firmware through the interface before displaying the result.
 
 ### PRU Firmware Design
-The firmware first initializes the PRU hardware, after which it waits until a command has been triggered through the interface. Upon triggering, the transmit data is set up based on the data ID code and the data is transmitted. The data ID code then waits until receiving all the data that depends on the data ID. The parsing over the received data then commences, which is again based on the data ID, and the interface is updated with the result. The CRC verification occurs next and the interface indicates command completion. The firmware then waits for the next command trigger from the interface.
+The firmware first initializes the PRU hardware,Then It check whether it is host trigger mode or periodic trigger mode, 
+In host trigger mode it waits until a command has been triggered through the interface,In periodic trigger mode firmware sets host trigger bit based on compare 3 event configured, Upon triggering the transmit data is set up based on the data ID code and the data is transmitted. The data ID code then waits until receiving all the data that depends on the data ID. The parsing over the received data then commences, which is again based on the data ID, and the interface is updated with the result. The CRC verification occurs next and the interface indicates command completion. The firmware then waits for the next command trigger from the interface.
 
 \image html Tamagawa_flowchart.JPG "Overview Flow Chart"