diff --git a/docs_src/docs/api_guide/components/position_sense/hdsl.md b/docs_src/docs/api_guide/components/position_sense/hdsl.md index 7c2db5f..7b2456a 100644 --- a/docs_src/docs/api_guide/components/position_sense/hdsl.md +++ b/docs_src/docs/api_guide/components/position_sense/hdsl.md @@ -8,26 +8,30 @@ The HDSL firmware running on ICSS-PRU provides a defined well interface to execu ## Features Supported -- Safe position -- Fast position, speed -- Communication status -- External pulse synchronization -- Register interface to be compatible with SICK HDSL FPGA IP Core (apart from the differences listed in \ref HDSL_EXCEPTIONS_LIST) -- Parameter channel communication +- Safe position +- Fast position, speed +- Communication status +- External pulse synchronization + - 1 to 10 frames per cycle + - 8 kHz to 50 kHz cycle frequency +- Register interface to be compatible with SICK HDSL FPGA IP Core (apart from the differences listed in \ref HDSL_EXCEPTIONS_LIST) +- Parameter channel communication - Short message - Long message -- Safety -- Two channels support on am243x-evm -- Single channel support on am243x-lp -- Tested with three different encoder makes (EDM35, EKS36, EKM36) +- Safety +- Pipeline Channel Data +- Three channel support using single PRU-ICSSG slice + - Three channel support on am243x-evm + - Two channel support on am243x-lp +- Tested with three different encoder makes (EDM35, EKS36, EKM36) ## Features Not Supported In general, peripherals or features not mentioned as part of "Features Supported" section are not supported, including the below - - 100m cable - - Three channel support using single PRU-ICSSG slice - - Pipeline Channel + - 100m cable + - Pipeline Channel Status + ## SysConfig Features @VAR_SYSCFG_USAGE_NOTE @@ -51,6 +55,58 @@ SysConfig can be used to configure things mentioned below: \subpage HDSL_EXCEPTIONS_LIST lists the exceptions TI's HDSL implementation when compared with SICK HDSL FPGA IP Core. Please note that all the corresponding register fields are not implemented. +## Datasheet + +### Synchronization Pulse Jitter + +- Synchronization Pulse Jitter is under 100ns. Please refer to the image below for jitter calculation waveforms. + +\image html hdsl_sync_mode_waveforms.png "HDSL Sync mode waveforms for 2 channels" +\image html hdsl_sync_mode_jitter.jpg "HDSL Sync mode jitter analysis" + +### Protocol Package Lengths with different ES and Sync Pulse Frequency values + +NOTE: Images below show TX_EN signal in "Red" and RX signal in "Yellow". + + + + + + + + + + + + + + +
ES Value + Cycle Time (in us) + Cycle Frequency (in kHz) + Observed Protocol Package Length (in us) +
1 + 25 + 40 + 25.06 +
1 + 20 + 50 + 19.942 +
2 + 25 + 40 + Between 12.26 and 12.80 +
5 + 62.5 + 16 + Between 11.94 and 12.60 +
10 + 125 + 8 + Between 11.94 and 12.90 +
+ ## Example \ref EXAMPLE_MOTORCONTROL_HDSL diff --git a/docs_src/docs/api_guide/components/position_sense/hdsl_design.md b/docs_src/docs/api_guide/components/position_sense/hdsl_design.md index 6241868..3739069 100644 --- a/docs_src/docs/api_guide/components/position_sense/hdsl_design.md +++ b/docs_src/docs/api_guide/components/position_sense/hdsl_design.md @@ -18,22 +18,38 @@ Refer PRU-ICSS chapter of AM64x/AM243x Technical Reference Manual ## Software Architecture -The firmware consists of two layers .On the one hand, there is the datalink layer, which is responsible for establishing a communication link to the encoder, monitoring the connection quality and preparing the data. -On the other hand, there is the transport layer that processes the data and determines what information is sent over the parameter channel. Figure "Layer Model" illustrates the relationship between the two layers. -The datalink layer assembles the information from the different channels and puts the data symbol by symbol to the channel buffers. The channel buffers are large enough to carry the data of a whole V-Frame for each channel. . -The transport layer controls the data sent over the parameter channel by setting the symbol to send for the next H-Frame in the parameter channel buffer. This buffer can carry only one symbol. +The Hiperface DSL function is implemented on one PRU-ICSSG to leave the other PRU-ICSSG for Industrial Ethernet functions. + +The firmware consists of two layers + +1. Datalink Layer : It is responsible for establishing a communication link to the encoder, monitoring the connection quality and preparing the data. It assembles the information from the different channels and puts the data symbol by symbol to the channel buffers. The channel buffers are large enough to carry the data of a whole vertical frame for each channel. +2. Transport Layer : It processes the data and determines what information is sent over the parameter channel. It controls the data sent over the parameter channel by setting the symbol to send for the next horizontal frame in the parameter channel buffer. This buffer can carry only one symbol. + Both layers have direct access to the register interface that is provided to the higher layers. +Figure "Layer Model" illustrates the relationship between the two layers. -\image html hdsl_layer_model.png "Layer Model " -Hiperface DSL specifies a state machine for the Receiver. This implementation features an additional state for loading new firmware to the PRU. Figure "State Machine" depicts the modified state machine. -Furthermore, this implementation exhibits three code sections in the firmware. The first one is for initializing the state machine up to the LOADFW state. +\image html hdsl_layer_model.png "Layer Model" + +### Overlay Scheme for TX-PRU + +Each PRU-ICSSG has two slices, and each slice has three cores : PRU, RTU-PRU and TX-PRU. The instruction memory for PRU, RTU-PRU and TX-PRU coreS is 12 kB, 8 kB and 6 kB respctively. Multi-channel implementation of Hiperface DSL is achieved by enabling load share mode of PRU-ICSSG where one core is responsible for one channel. One PRU-ICSSG slice supports three peripheral interfaces for HDSL. Mapping is fixed to channel 0 with RTU-PRU, channel 1 with TX-PRU. To implement an equivalent data link layer and transport layer as the reference IP-core for the Hiperface DSL on FPGA, the instruction memory for TX-PRU is not enough. Hence a code overlay scheme is required only for TX-PRU core, which is only needed if channel 2 is enabled. + +For PRU and RTU-PRU, the firmware for Hiperface DSL fully fits into instruction memory. The firmware for TX-PRU is split into following three code sections based on initialization and normal operation: + +1. Initialization specific code +2. Normal operation code +3. Common code needed during initialization and normal operation + +Part 3 is loaded directly into instruction memory (IMEM) of TX-PRU by ARM core as it will be needed in all states. Part 1 and Part 2 of firmware for TX-PRU are stored in PRU-ICSS Data Memory (DMEM) by ARM core. During initialization (LOADFW1 state shown in next section), part 1 is copied into instruction memory (IMEM) of TX-PRU from Data Memory (DMEM) by RTU-PRU core. After initialization is complete (LOADFW2 state shown in next section), part 2 is copied into instruction memory (IMEM) of TX-PRU from Data Memory (DMEM) by RTU-PRU core. + +### State Machine + +Hiperface DSL specifies a state machine for the Receiver. This implementation features two additional states for loading firmware to the TX-PRU from RTU-PRU. Figure "State Machine" depicts the modified state machine. \image html hdsl_state_machine.png "State Machine" -The second section contains datalink functionalities that are needed for the startup phase as well as for the normal workflow. The transport layer functionalities reside in the third section. - ### Datalink Layer The datalink layer is responsible for handling the communication link to the encoder. This includes the sampling, cable delay compensation, DC line balancing, encoding and decoding of data and the monitoring of the connection quality. @@ -68,7 +84,17 @@ The RSSI is calculated by determining the number of samples between two edges du A 16bit CRC verification of the data is used on multiple occasions. It is used for the vertical channel, secondary channel and messages. In order to distribute the computation load equally over all H-Frames, the firmware calculates a running CRC for those data (except for short messages). The algorithm uses a LUT with 256 entries and 2 bytes per entry, whereas each entry is the 16bit CRC for the corresponding LUT index. The basic approach for the calculation of the 16bit CRC is shown as C code in the following: -uint16_t calc_crc(uint8_t *data, uint32_t size) { uint16_t crc = 0; uint32_t i; for(i = 0; i < size; ++i) { crc = ((*data) << 8) ^ crc; crc = lut[crc>>8] ^ (crc << 8); } return (crc ^ 0xff); } + uint16_t calc_crc(uint8_t *data, uint32_t size) + { + uint16_t crc = 0; + uint32_t i; + for(i = 0; i < size; ++i) + { + crc = ((*data) << 8) ^ crc; + crc = lut[crc>>8] ^ (crc << 8); + } + return (crc ^ 0xff); + } ### Transport Layer @@ -110,24 +136,29 @@ It is possible that these calculations lead to the excess of the maximum or mini The algorithm is given as C code in the following: - /* EXTRA_SIZE equals the number of bits for the EXTRA window minus 1 */ - if(EXTRA_EDGE == 0) - TIME_REST += 8; - short b = (EXTRA_SIZE << 3) + TIME_REST; - short overhead = (EXTRA_SIZE << 3) + 8 - TIME_EXTRA_WINDOW; - EXTRA_SIZE = (b - overhead) >> 3; - TIME_REST = (b - overhead) - (EXTRA_SIZE << 3); + /* EXTRA_SIZE equals the number of bits for the EXTRA window minus 1 */ + if(EXTRA_EDGE == 0) + { + TIME_REST += 8; + } - if(EXTRA_SIZE < 3) { - EXTRA_SIZE += 6; - NUM_STUFFING -= 1; - TIME_EXTRA_WINDOW += (8*6); - } -if(EXTRA_SIZE > 8) { - EXTRA_SIZE -= 6; - NUM_STUFFING += 1; - TIME_EXTRA_WINDOW -= (8*6); - } + short b = (EXTRA_SIZE << 3) + TIME_REST; + short overhead = (EXTRA_SIZE << 3) + 8 - TIME_EXTRA_WINDOW; + EXTRA_SIZE = (b - overhead) >> 3; + TIME_REST = (b - overhead) - (EXTRA_SIZE << 3); + + if(EXTRA_SIZE < 3) + { + EXTRA_SIZE += 6; + NUM_STUFFING -= 1; + TIME_EXTRA_WINDOW += (8*6); + } + if(EXTRA_SIZE > 8) + { + EXTRA_SIZE -= 6; + NUM_STUFFING += 1; + TIME_EXTRA_WINDOW -= (8*6); + } EXTRA_EDGE represents the TIME_REST value in a format that can be pushed to the TX FIFO for transmission. For instance, if TIME_REST is 4, EXTRA_EDGE is 0xf0. The edge would be in the middle of the bit duration. The value NUM_STUFFING gives the number of stuffing blocks (each block consist of 6 bits). @@ -137,7 +168,3 @@ For further improvement of the synchronization, the time difference (∆t) betwe \imageStyle{hdsl_external_sync_sample_edge.png,width:40%} \image html hdsl_external_sync_sample_edge.png "Time difference between External Pulse and Sample Edge" - -Sync pulse jitter is under 100ns. Please refer to the image below for jitter calculation waveforms. -\image html hdsl_sync_mode_waveforms.png "HDSL Sync mode waveforms for 2 channels" -\image html hdsl_sync_mode_jitter.jpg "HDSL Sync mode jitter analysis" diff --git a/docs_src/docs/api_guide/components/position_sense/hdsl_exceptions_list.md b/docs_src/docs/api_guide/components/position_sense/hdsl_exceptions_list.md index 4a07901..3dac251 100644 --- a/docs_src/docs/api_guide/components/position_sense/hdsl_exceptions_list.md +++ b/docs_src/docs/api_guide/components/position_sense/hdsl_exceptions_list.md @@ -3,7 +3,7 @@ Notable exceptions in TI HDSL Solution when compared with SICK HDSL MASTER IP Core release version 1.07 are described below: 1. SPI interface is not available to access the HDSL Master. Registers are present in Data Memory of Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS), which can be accessed directly by the ARM processor core. -2. Pipeline for SensorHub Channel Data is not available. +2. Pipeline Status for SensorHub Channel is not available. Pipeline data is updated for each horizontal frame. 3. Control signals similar to SICK HDSL MASTER IP Core are not available, except SYNC signal. Instead of INTERRUPT signal, interrupts are triggered to ARM processor core. 4. Test signals similar to SICK HDSL MASTER IP Core are not available. 5. TI HDSL Solution's register map is register compatible with SICK HDSL MASTER IP Core release version 1.07, with few exceptions listed below: @@ -49,7 +49,6 @@ Notable exceptions in TI HDSL Solution when compared with SICK HDSL MASTER IP Co PIPE_S
- PIPE_D **Not available in TI HDSL Solution** diff --git a/docs_src/docs/api_guide/components/position_sense/hdsl_registers_list.md b/docs_src/docs/api_guide/components/position_sense/hdsl_registers_list.md index b18364f..da2ed15 100644 --- a/docs_src/docs/api_guide/components/position_sense/hdsl_registers_list.md +++ b/docs_src/docs/api_guide/components/position_sense/hdsl_registers_list.md @@ -1063,7 +1063,7 @@ TI HDSL Solution's register map is compatible with SICK HDSL MASTER IP Core rele 0x2E SensorHub Channel Data -
**NOTE : Not available in TI HDSL Solution** + 8 bit value of the SensorHub Channel Data PC_DATA diff --git a/docs_src/docs/api_guide/device/am243x/includes.cfg b/docs_src/docs/api_guide/device/am243x/includes.cfg index a0a67a9..8a3b093 100644 --- a/docs_src/docs/api_guide/device/am243x/includes.cfg +++ b/docs_src/docs/api_guide/device/am243x/includes.cfg @@ -11,6 +11,7 @@ INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/main_page/main_page.m INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/migration_guides/mcusdk_migration_guide.md INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/release_notes.md INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/release_notes_09_00_00.md +INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/release_notes_09_01_00.md @INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/examples.cfg @INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/components.cfg @INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/dcl/dcl.cfg diff --git a/docs_src/docs/api_guide/device/am243x/release_notes.md b/docs_src/docs/api_guide/device/am243x/release_notes.md index d4c7104..b74fe31 100644 --- a/docs_src/docs/api_guide/device/am243x/release_notes.md +++ b/docs_src/docs/api_guide/device/am243x/release_notes.md @@ -5,4 +5,5 @@ Refer the below pages for release specific information - \subpage RELEASE_NOTES_09_00_00_PAGE +- \subpage RELEASE_NOTES_09_01_00_PAGE diff --git a/docs_src/docs/api_guide/device/am243x/release_notes_09_01_00.md b/docs_src/docs/api_guide/device/am243x/release_notes_09_01_00.md new file mode 100644 index 0000000..3ebbedc --- /dev/null +++ b/docs_src/docs/api_guide/device/am243x/release_notes_09_01_00.md @@ -0,0 +1,359 @@ +# Release Notes 09.01.00 {#RELEASE_NOTES_09_01_00_PAGE} + +[TOC] + +\attention Also refer to individual module pages for more details on each feature, unsupported features, important usage guidelines. + +\attention For release notes of Industrial Communications SDK and MCU+ SDK, please refer to @VAR_SOC_NAME Industrial Communications SDK Release Notes 09.01.00 and @VAR_SOC_NAME MCU+ SDK Release Notes 09.01.00 respectively. + +\note The examples will show usage of SW modules and APIs on a specific CPU instance and OS combination. \n + Unless noted otherwise, the SW modules would work in both FreeRTOS and NORTOS environment. \n + Unless noted otherwise, the SW modules would work on any of the R5F's present on the SOC. \n + Unless noted otherwise, the SW modules would work on all supported EVMs \n + +\note Tamagawa over SoC UART example is not supported for AM243x + +## New in this Release + +Feature | Module +------------------------------------------------------------------------------------------------|----------------------------------- +Three channel support with one PRU-ICSSG Slice | Position Sense HDSL +SYNC Mode support for 1 to 10 frames per cycle and 8 kHz to 50 kHz cycle frequency | Position Sense HDSL +API support for Parameter Channel Long Message Read and Write | Position Sense HDSL +Add support for PIPE_D register for SensorHub Channel | Position Sense HDSL + +## Device and Validation Information + +SOC | Supported CPUs | Boards | Host PC +-------|-----------------|-------------------------------------------------------------------------------------------------------------|----------------------------------- +AM243x | R5F | AM243x GP EVM (referred to as am243x-evm in code), \n AM243x LAUNCHPAD (referred to as am243x-lp in code) | Windows 10 64b or Ubuntu 18.04 64b + +## Tools, Compiler and Other Open Source SW Module Information + +Tools / SW module | Supported CPUs | Version +------------------------|----------------|----------------------- +Code Composer Studio | R5F, M4F, A53 | @VAR_CCS_VERSION +SysConfig | R5F, M4F, A53 | @VAR_SYSCFG_VERSION, build @VAR_SYSCFG_BUILD +TI ARM CLANG | R5F, M4F | @VAR_TI_ARM_CLANG_VERSION +FreeRTOS Kernel | R5F, M4F, A53 | @VAR_FREERTOS_KERNEL_VERSION +FreeRTOS SMP Kernel | A53 | @VAR_FREERTOS_SMP_KERNEL_VERSION + +## Key Features + + + + + + + + + +### Position Sense + +Module | Supported CPUs | SysConfig Support | OS Support | Key features tested | Key features not tested +-------------|----------------|-------------------|-------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------|----------------------------------------------------------------------------------- +EnDat | R5F | YES | FreeRTOS, NORTOS | Single channel, Multi channel, Continuous mode for single channel, Load share mode, Recovery Time for 2.2 command set, Boosterpack with AM243x-LP | Encoder receive communication command +HDSL | R5F | YES | FreeRTOS, NORTOS | Freerun mode(300MHz,225MHz), Sync mode(225MHz), Short Message Read & Write, Long Message Read & Write, Boosterpack with AM243x-LP | Long cables +Tamagawa | R5F | YES | FreeRTOS, NORTOS | Absolute position, Encoder ID, Reset, EEPROM Read, EEPROM Write, 2.5 Mbps and 5 Mbps Encoder Support, Boosterpack with AM243x-LP | - + +### Current Sense + + +Module | Supported CPUs | SysConfig Support | OS Support | Key features tested | Key features not tested +-------------|----------------|-------------------|-------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------|----------------------------------------------------------------------------------- +%SDFM | R5F | YES | FreeRTOS, NORTOS | 3 %SDFM channels on single PRU core, %SDFM Sync with EPWM, Overcurrent, single normal current sampling per PWM cycle, Double normal current sampling per PWM cycle, High and Low threshold comparator, Tested with SDFM clock from ECAP, Tested with 5MHz Clock from EPWM | - + + +## Fixed Issues + + + + + + + + + + + + + + + + + + + + +
ID + Head Line + Module + Applicable Releases + Resolution/Comments +
PINDSW-6628 + HDSL: Reset value of PRST bit is not correct + Position Sense HDSL + 9.0 + - +
PINDSW-6629 + HDSL: SSUM bit in EVENT_S is not set when SUMMARY is non-zero + Position Sense HDSL + 9.0 + SSUM bit in EVENT_S was masked with MASK_SUM which was incorrect. +
PINDSW-6931 + Tamagawa: Firmware build failing + Position Sense Tamagawa + 9.0 + - +
PINDSW-6944 + HDSL: QM increment is not correct + Position Sense HDSL + 9.0 + QM updates for Safe Channel 2 were incorrect. +
PINDSW-7048 + HDSL: SCE bit in ONLINE STATUS 1 gets cleared before seeing a correct CRC in safe channel + Position Sense HDSL + 9.0 + - +
PINDSW-7126 + HDSL: Protocol reset is seen multiple times with certain encoders + Position Sense HDSL + 9.0 + - +
PINDSW-7129 + HDSL: Stuffing Data in Learn state is incorrect with Free Run Mode + Position Sense HDSL + 9.0 + - +
PINDSW-7157 + HDSL : Sync mode does not work for ES value greater than 1 + Position Sense HDSL + 9.0 + - +
+ +## Known Issues + + + + + + + + + + + + + + + + + + + + +
ID + Head Line + Module + Applicable Releases + Workaround +
PINDSW-5537 + HDSL not working with 225 MHz PRU-ICSSG Core Clock Frequency + Position Sense HDSL + 9.0 onwards + Use 300 MHz frequency for PRU-ICSSG Core Clock +
PINDSW-5690 + HDSL: EDGE register is not updated + Position Sense HDSL + 9.0 onwards + - +
PINDSW-6486 + HDSL: RSSI register shows higher values than expected for a non-noisy setup + Position Sense HDSL + 9.0 onwards + - +
PINDSW-6544 + %SDFM: Incorrect samples seen intermittently with EPWM as %SDFM clock + Current Sense %SDFM + 9.0 onwards + Use 5MHz %SDFM clock from EPWM1 (tested with 5MHz clock from EPWM) or use PRU-ICSSG ECAP as %SDFM clock source +
PINDSW-6630 + HDSL: POS bit is not set during initial fast position alignment + Position Sense HDSL + 9.0 onwards + - +
PINDSW-7130 + HDSL: Few protocol resets seen during initialization with Free Run mode on AM243x-LP + Position Sense HDSL + 9.0 onwards + - +
PINDSW-7158 + HDSL: Reset Value of SSUM bit is not correct + Position Sense HDSL + 9.0 onwards + - +
PINDSW-7163 + HDSL: Trailer data contains 4 zeros instead of 5 + Position Sense HDSL + 9.0 onwards + - +
+ + + +## Limitations + + + + + +
ID + Head Line + Module + Reported in Release + Applicable Devices + Workaround +
MCUSDK-208 + gmake with -j can sometimes lock up Windows command prompt + Build + 7.3.0 + AM64x, AM243x + Use bash for windows as part of git for windows or don't use -j option +
+ +## Upgrade and Compatibility Information {#UPGRADE_AND_COMPATIBILITY_INFORMATION_9_1_0} + + + +This section lists changes which could affect user applications developed using older SDK versions. +Read this carefully to see if you need to do any changes in your existing application when migrating to this SDK version relative to +previous SDK version. Also refer to older SDK version release notes to see changes in +earlier SDKs. + + + +### Examples + + + + + + +
Module + Affected API + Change + Additional Remarks +
+ + + +
+ +### Drivers + + + + + + + + +
Module + Affected API + Change + Additional Remarks +
Position Sense HDSL + \ref HDSL_write_pc_buffer + Updated parameters to take only buffer offset and data, instead of data for all buffers. + - +
diff --git a/docs_src/docs/api_guide/device/am263x/includes.cfg b/docs_src/docs/api_guide/device/am263x/includes.cfg index 42fcfb0..af8b12e 100644 --- a/docs_src/docs/api_guide/device/am263x/includes.cfg +++ b/docs_src/docs/api_guide/device/am263x/includes.cfg @@ -11,6 +11,7 @@ INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/main_page/main_page.m INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/migration_guides/mcusdk_migration_guide.md INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/release_notes.md INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/release_notes_09_00_00.md +INPUT += $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/release_notes_09_01_00.md @INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/examples.cfg @INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/device/$(DEVICE)/components.cfg @INCLUDE = $(MOTOR_CONTROL_SDK_PATH)/docs_src/docs/api_guide/components/dcl/dcl.cfg diff --git a/docs_src/docs/api_guide/device/am263x/release_notes.md b/docs_src/docs/api_guide/device/am263x/release_notes.md index d4c7104..b74fe31 100644 --- a/docs_src/docs/api_guide/device/am263x/release_notes.md +++ b/docs_src/docs/api_guide/device/am263x/release_notes.md @@ -5,4 +5,5 @@ Refer the below pages for release specific information - \subpage RELEASE_NOTES_09_00_00_PAGE +- \subpage RELEASE_NOTES_09_01_00_PAGE diff --git a/docs_src/docs/api_guide/device/am263x/release_notes_09_01_00.md b/docs_src/docs/api_guide/device/am263x/release_notes_09_01_00.md new file mode 100644 index 0000000..5614c95 --- /dev/null +++ b/docs_src/docs/api_guide/device/am263x/release_notes_09_01_00.md @@ -0,0 +1,197 @@ +# Release Notes 09.01.00 {#RELEASE_NOTES_09_01_00_PAGE} + +[TOC] + +\attention Also refer to individual module pages for more details on each feature, unsupported features, important usage guidelines. + +\attention For release notes of Industrial Communications SDK and MCU+ SDK, please refer to @VAR_SOC_NAME Industrial Communications SDK Release Notes 09.01.00 and @VAR_SOC_NAME MCU+ SDK Release Notes 09.01.00 respectively. + +\note The examples will show usage of SW modules and APIs on a specific CPU instance and OS combination. \n + Unless noted otherwise, the SW modules would work in both FreeRTOS and NORTOS environment. \n + Unless noted otherwise, the SW modules would work on any of the R5F's present on the SOC. \n + Unless noted otherwise, the SW modules would work on all supported EVMs \n + +## New in this Release + +Feature | Module +------------------------------------------------------------------------------------------------|----------------------------------- + +## Device and Validation Information + +SOC | Supported CPUs | EVM | Host PC +------|-----------------|------------------------------------------------------------------------------|----------------------------------------- +AM263x| R5F | AM263x ControlCard Revision E1 (referred to as am263x-cc in code). \n | Windows 10 64b or Ubuntu 18.04 64b +AM263x| R5F | AM263x LaunchPad Revision E2 (referred to as am263x-lp in code) | Windows 10 64b or Ubuntu 18.04 64b + +## Tools, Compiler and Other Open Source SW Module Information + +Tools | Supported CPUs | Version +------------------------|----------------|-------------------------------------------------------------- +Code Composer Studio | R5F | @VAR_CCS_VERSION_AM263X +SysConfig | R5F | @VAR_SYSCFG_VERSION_AM263X, build @VAR_SYSCFG_BUILD_AM263X +TI ARM CLANG | R5F | @VAR_TI_ARM_CLANG_VERSION +FreeRTOS Kernel | R5F | @VAR_FREERTOS_KERNEL_VERSION + +## Key Features + +### Position Sense + +Module | Supported CPUs | SysConfig Support | OS Support | Key features tested | Key features not tested +-------------|----------------|-------------------|-------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------|----------------------------------------------------------------------------------- +Tamagawa | R5F | YES | FreeRTOS | Absolute position, Encoder ID, Reset, EEPROM Read, EEPROM Write, 2.5 Mbps and 5 Mbps Encoder Support | - + + + + + + + +## Limitations + + + + + +
ID + Head Line + Module + Reported in Release + Applicable Devices + Workaround +
MCUSDK-208 + gmake with -j can sometimes lock up Windows command prompt + Build + 7.3.0 + AM64x, AM243x + Use bash for windows as part of git for windows or don't use -j option +
+ + + + + + + + + + diff --git a/docs_src/docs/api_guide/examples/hdsl_example.md b/docs_src/docs/api_guide/examples/hdsl_example.md index e5e360a..44df86b 100644 --- a/docs_src/docs/api_guide/examples/hdsl_example.md +++ b/docs_src/docs/api_guide/examples/hdsl_example.md @@ -71,9 +71,9 @@ This example also allows the capability to save the HDSL register data into memo ---------------|----------- CPU + OS | r5fss0-0 freertos ICSSG | ICSSG0 - PRU | PRU1 + PRU | RTU-PRU1, PRU1, TXPRU1 (based on number of channels enabled) Toolchain | ti-arm-clang - Board | @VAR_BOARD_NAME_LOWER (2 channel and 1 channel examples), @VAR_LP_BOARD_NAME_LOWER (1 channel example) + Board | @VAR_BOARD_NAME_LOWER (2 channel and 1 channel examples), @VAR_LP_BOARD_NAME_LOWER (2 channel and 1 channel examples) Example folder | examples/position_sense/hdsl_diagnostic \endcond diff --git a/docs_src/docs/api_guide/images/images.pptx b/docs_src/docs/api_guide/images/images.pptx index 45227e0..78287b9 100644 Binary files a/docs_src/docs/api_guide/images/images.pptx and b/docs_src/docs/api_guide/images/images.pptx differ diff --git a/docs_src/docs/api_guide/images/position_sense/hdsl_layer_model.png b/docs_src/docs/api_guide/images/position_sense/hdsl_layer_model.png index aea1114..d909c86 100644 Binary files a/docs_src/docs/api_guide/images/position_sense/hdsl_layer_model.png and b/docs_src/docs/api_guide/images/position_sense/hdsl_layer_model.png differ diff --git a/docs_src/docs/api_guide/images/position_sense/hdsl_state_machine.png b/docs_src/docs/api_guide/images/position_sense/hdsl_state_machine.png index 6a88eb9..535d481 100644 Binary files a/docs_src/docs/api_guide/images/position_sense/hdsl_state_machine.png and b/docs_src/docs/api_guide/images/position_sense/hdsl_state_machine.png differ