diff --git a/source/position_sense/hdsl/firmware/datalink.asm b/source/position_sense/hdsl/firmware/datalink.asm index bace865..6380a16 100644 --- a/source/position_sense/hdsl/firmware/datalink.asm +++ b/source/position_sense/hdsl/firmware/datalink.asm @@ -116,7 +116,7 @@ datalink_wait_vsynch: lbco ®_TMP0, MASTER_REGS_CONST, EVENT_S, 2 set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_FRES ;save events - sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1 qbbc update_events_no_int0, REG_TMP0.b1, EVENT_S_FRES ; generate interrupt ldi r31.w0, PRU0_ARM_IRQ4 diff --git a/source/position_sense/hdsl/firmware/datalink_init.asm b/source/position_sense/hdsl/firmware/datalink_init.asm index 76f26d9..2854f7a 100644 --- a/source/position_sense/hdsl/firmware/datalink_init.asm +++ b/source/position_sense/hdsl/firmware/datalink_init.asm @@ -114,7 +114,7 @@ update_events_no_int15: lbco ®_TMP0, MASTER_REGS_CONST, EVENT_S, 2 set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_PRST ;save events - sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1 qbbc update_events_no_int22, REG_TMP0.b1, EVENT_S_PRST ; generate interrupt ldi r31.w0, PRU0_ARM_IRQ4 diff --git a/source/position_sense/hdsl/firmware/defines.inc b/source/position_sense/hdsl/firmware/defines.inc index 6423ab2..18a1c9c 100644 --- a/source/position_sense/hdsl/firmware/defines.inc +++ b/source/position_sense/hdsl/firmware/defines.inc @@ -34,7 +34,7 @@ ; bit7..4 major number FIRMWARE_VERSION_MAJOR .set 0x0 ; bit3..0 minor number -FIRMWARE_VERSION_MINOR .set 0x8 +FIRMWARE_VERSION_MINOR .set 0x9 ICSS_FIRMWARE_RELEASE .set ((FIRMWARE_VERSION_MAJOR << 4) | (FIRMWARE_VERSION_MINOR << 0)) diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h index 2c19c76..e450daf 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h @@ -1068,20 +1068,20 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0xd105c008, 0x915818c0, 0x5100c007, -0x1f058000, +0x1f050000, 0x81541800, 0x2400080d, 0x040d6666, 0x23032cd1, 0x79000014, -0x1d058000, +0x1d050000, 0x81541800, 0x91541800, 0x69fd6204, -0x1f028000, +0x1f020000, 0x81541800, 0x79000002, -0x1d028000, +0x1d020000, 0x15e06262, 0x2ed00381, 0xd1060204, @@ -1123,15 +1123,15 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x91503802, 0x51000009, 0x1f060202, -0x1f060242, +0x1f064242, 0x913d1880, 0x1f060000, -0x813d1880, +0x813d1800, 0xc9062002, 0x2400269f, 0x79000003, 0x1d060202, -0x1d060242, +0x1d064242, 0x81503802, 0x10abab8d, 0x21021100, @@ -1650,7 +1650,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = { 0x81080580, 0x240003c0, 0x810605c0, -0x24000800, +0x24000900, 0x810b1800, 0x81441800, 0x2eff8383, diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h index 431e917..531c271 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h @@ -1184,20 +1184,20 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0xd105c008, 0x915818c0, 0x5100c007, -0x1f058000, +0x1f050000, 0x81541800, 0x2400080d, 0x040d6666, 0x23034bd1, 0x79000014, -0x1d058000, +0x1d050000, 0x81541800, 0x91541800, 0x69fd6204, -0x1f028000, +0x1f020000, 0x81541800, 0x79000002, -0x1d028000, +0x1d020000, 0x15e06262, 0x2ed00381, 0xd1060204, @@ -1239,15 +1239,15 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x91503802, 0x51000009, 0x1f060202, -0x1f060242, +0x1f064242, 0x913d1880, 0x1f060000, -0x813d1880, +0x813d1800, 0xc9062002, 0x2400269f, 0x79000003, 0x1d060202, -0x1d060242, +0x1d064242, 0x81503802, 0x10abab8d, 0x21021100, @@ -1766,7 +1766,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = { 0x81080580, 0x240003c0, 0x810605c0, -0x24000800, +0x24000900, 0x810b1800, 0x81441800, 0x2eff8383, diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h index e031ecb..a851b43 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h @@ -1068,20 +1068,20 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0xd105c008, 0x915818c0, 0x5100c007, -0x1f058000, +0x1f050000, 0x81541800, 0x2400080d, 0x040d6666, 0x23032cd1, 0x79000014, -0x1d058000, +0x1d050000, 0x81541800, 0x91541800, 0x69fd6204, -0x1f028000, +0x1f020000, 0x81541800, 0x79000002, -0x1d028000, +0x1d020000, 0x15e06262, 0x2ed00381, 0xd1060204, @@ -1123,15 +1123,15 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x91503802, 0x51000009, 0x1f060202, -0x1f060242, +0x1f064242, 0x913d1880, 0x1f060000, -0x813d1880, +0x813d1800, 0xc9062002, 0x2400269f, 0x79000003, 0x1d060202, -0x1d060242, +0x1d064242, 0x81503802, 0x10abab8d, 0x21021100, @@ -1651,7 +1651,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = { 0x81100580, 0x240003c0, 0x810605c0, -0x24000800, +0x24000900, 0x810b1800, 0x81441800, 0x2eff8383, diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h index 6bf8094..a2670b9 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h @@ -1184,20 +1184,20 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0xd105c008, 0x915818c0, 0x5100c007, -0x1f058000, +0x1f050000, 0x81541800, 0x2400080d, 0x040d6666, 0x23034bd1, 0x79000014, -0x1d058000, +0x1d050000, 0x81541800, 0x91541800, 0x69fd6204, -0x1f028000, +0x1f020000, 0x81541800, 0x79000002, -0x1d028000, +0x1d020000, 0x15e06262, 0x2ed00381, 0xd1060204, @@ -1239,15 +1239,15 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x91503802, 0x51000009, 0x1f060202, -0x1f060242, +0x1f064242, 0x913d1880, 0x1f060000, -0x813d1880, +0x813d1800, 0xc9062002, 0x2400269f, 0x79000003, 0x1d060202, -0x1d060242, +0x1d064242, 0x81503802, 0x10abab8d, 0x21021100, @@ -1767,7 +1767,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = { 0x81100580, 0x240003c0, 0x810605c0, -0x24000800, +0x24000900, 0x810b1800, 0x81441800, 0x2eff8383, diff --git a/source/position_sense/hdsl/firmware/transport.asm b/source/position_sense/hdsl/firmware/transport.asm index 9fd7884..fbe3af0 100644 --- a/source/position_sense/hdsl/firmware/transport.asm +++ b/source/position_sense/hdsl/firmware/transport.asm @@ -119,7 +119,7 @@ transport_on_v_frame: lbco ®_TMP0, MASTER_REGS_CONST, EVENT_S, 2 set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_SCE ;save events - sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1 qbbc update_events_no_int4, REG_TMP0.b1, EVENT_S_SCE ; generate interrupt_s ldi r31.w0, PRU0_ARM_IRQ4 @@ -152,7 +152,7 @@ push_1B: lbco ®_TMP0, MASTER_REGS_CONST, EVENT_S, 2 set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_VPOS ;save events - sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1 qbbc update_events_no_int5, REG_TMP0.b1, EVENT_S_VPOS ; generate interrupt_s ldi r31.w0, PRU0_ARM_IRQ4 @@ -283,14 +283,14 @@ transport_on_v_frame_2: lbco ®_TMP0.w2, MASTER_REGS_CONST, CRC_SEC_TEMP, 2 qbeq check_for_slave_error_on_secondary_channel, REG_TMP0.w2, 0 ; set SCE2 bit in ONLINE_STATUS_2 - set REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2 + set REG_TMP0.b0, REG_TMP0.b0, ONLINE_STATUS_2_SCE2 sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 QM_SUB 8 transport_on_v_frame_dont_update_qm_secondary_channel: qba transport_on_v_frame_2_exit check_for_slave_error_on_secondary_channel: ; clear SCE2 bit in ONLINE_STATUS_2 - clr REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_SCE2 + clr REG_TMP0.b0, REG_TMP0.b0, ONLINE_STATUS_2_SCE2 sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 ; No QM updates for CRC check success with safe channel 2 lbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 @@ -298,11 +298,11 @@ check_for_slave_error_on_secondary_channel: ; assumption: r21.b3 contains the first byte of secondary vertical channel qbne transport_on_v_frame_no_vpos2_error, REG_TMP2.b3, K29_7 ; set VPOS2 bit in ONLINE_STATUS_2 - set REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_VPOS2 + set REG_TMP0.b0, REG_TMP0.b0, ONLINE_STATUS_2_VPOS2 sbco ®_TMP0.b0, MASTER_REGS_CONST, ONLINE_STATUS_2_H, 1 qba transport_on_v_frame_vpos2_error_exit transport_on_v_frame_no_vpos2_error: - clr REG_TMP0.b0, REG_TMP0.w0, ONLINE_STATUS_2_VPOS2 + clr REG_TMP0.b0, REG_TMP0.b0, ONLINE_STATUS_2_VPOS2 transport_on_v_frame_vpos2_error_exit: ; store the data from secondary channel @@ -382,12 +382,12 @@ summary_no_int: lbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 3 qbeq online_status_sum_clear, REG_TMP0.b0, 0x00 set REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM - set REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM + set REG_TMP2.b2, REG_TMP2.b2, ONLINE_STATUS_1_SSUM ;set SSUM in EVENT_S and generate interrupt_s lbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 2 set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_SSUM ;save events - sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 2 + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1 qbbc update_events_no_int17, REG_TMP0.b1, EVENT_S_SSUM ; generate interrupt_s ldi r31.w0, PRU0_ARM_IRQ4 @@ -395,7 +395,7 @@ update_events_no_int17: qba online_status_sum_save online_status_sum_clear: clr REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM - clr REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM + clr REG_TMP2.b2, REG_TMP2.b2, ONLINE_STATUS_1_SSUM online_status_sum_save: sbco ®_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 3 @@ -554,7 +554,7 @@ transport_layer_received_short_msg: lbco ®_TMP0, MASTER_REGS_CONST, EVENT_S, 2 set REG_TMP0.w0, REG_TMP0.w0, EVENT_S_FRES ;save events - sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1 qbbc update_events_no_int100, REG_TMP0.b1, EVENT_S_FRES ; generate interrupt ldi r31.w0, PRU0_ARM_IRQ @@ -578,7 +578,7 @@ transport_layer_short_msg_recv_read: lbco ®_TMP0, MASTER_REGS_CONST, EVENT_S, 2 set REG_TMP0.w0, REG_TMP0.w0, EVENT_S_FRES ;save events - sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1 qbbc update_events_no_int10, REG_TMP0.b1, EVENT_S_FRES ; generate interrupt ldi r31.w0, PRU0_ARM_IRQ @@ -702,7 +702,7 @@ update_events_no_int19: lbco ®_TMP0, MASTER_REGS_CONST, EVENT_S, 2 set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_MIN ;save events - sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1 qbbc update_events_no_int20, REG_TMP0.b1, EVENT_S_MIN ; generate interrupt ldi r31.w0, PRU0_ARM_IRQ4 @@ -935,7 +935,7 @@ update_events_no_int3: lbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 2 set REG_TMP0.b0, REG_TMP0.b0, EVENT_S_QMLW ;save events - sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_S, 1 + sbco ®_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1 qbbc update_events_no_int16, REG_TMP0.b1, EVENT_S_QMLW ; generate interrupt_s ldi r31.w0, PRU0_ARM_IRQ4