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Pull request #59: am64x/am243x: HDSL- multiple sync frequencies support

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Merge in PINDSW/motor_control_sdk from a0497643_PINDSW-7049_hdsl_sync_mode_multiple_frequencies to next

* commit '4aa9cfe08d63dac6bf46725ba6b82da48206c7e5':
  am64x/am243x: hdsl: Fix for multiple sync frequency
This commit is contained in:
Rajul Bhambay 2023-12-07 03:33:48 -06:00 committed by Pratheesh Gangadhar TK
commit 9998f7deb4
7 changed files with 146 additions and 78 deletions
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91
examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c
View File

@ -60,7 +60,12 @@
#include <position_sense/hdsl/include/hdsl_drv.h>
#include <position_sense/hdsl/include/pruss_intc_mapping.h>
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000)
/* PRU clock frequency =225Mhz */
#define PRU_CLK_FREQ_225M 225000000
/* PRU clock frequency =300Mhz */
#define PRU_CLK_FREQ_300M 300000000
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==PRU_CLK_FREQ_225M)
#include <position_sense/hdsl/firmware/hdsl_master_icssg_freerun_225_mhz_bin.h>
#include <position_sense/hdsl/firmware/hdsl_master_icssg_sync_225_mhz_bin.h>
/* Divide factor for normal clock (default value for 225 MHz=23) */
@ -69,7 +74,7 @@
#define DIV_FACTOR_OVERSAMPLED 2
#endif
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000)
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==PRU_CLK_FREQ_300M)
#include <position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h>
#include <position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h>
#include <position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h>
@ -83,6 +88,8 @@
#define HDSL_MULTI_CHANNEL
#endif
#define SYNC_PULSE_WAIT_CLK_CYCLES 5505
/* Divide factor for normal clock (default value for 300 MHz=31) */
#define DIV_FACTOR_NORMAL 31
/* Divide factor for oversampled clock (default value for 300 MHz=3) */
@ -97,6 +104,12 @@
/* Oversample rate 8*/
#define OVERSAMPLE_RATE 7
/* max cycle time for transmission of dsl frame*/
#define MAX_SYNC_CYCLE_TIME 27
/* min cycle time for transmission of dsl frame*/
#define MIN_SYNC_CYCLE_TIME 12
#define HDSL_EN (0x1 << 26)
/* OCP as clock, div 32 */
#define HDSL_TX_CFG (0x10 | (DIV_FACTOR_NORMAL << 16))
@ -134,24 +147,6 @@
/* Function Declarations */
/* ========================================================================== */
#if !defined(HDSL_MULTI_CHANNEL) && defined(_DEBUG_)
void App_udmaEventCb(Udma_EventHandle eventHandle, uint32_t eventType, void *appData);
static void App_udmaTrpdInit(Udma_ChHandle chHandle,
uint8_t *trpdMem,
const void *destBuf,
const void *srcBuf,
uint32_t length);
void udma_copy(uint8_t *srcBuf, uint8_t *destBuf, uint32_t length);
static void HDSL_IsrFxn();
#ifndef HDSL_MULTI_CHANNEL
void traces_into_memory(HDSL_Handle hdslHandle);
#endif
void sync_calculation(HDSL_Handle hdslHandle);
void process_request(HDSL_Handle hdslHandle,int32_t menu);
@ -184,12 +179,28 @@ void indirect_write_rid0_length8(HDSL_Handle hdslHandle);
static int get_menu(void);
uint32_t read_encoder_resolution(HDSL_Handle hdslHandle);
#ifdef HDSL_AM64xE1_TRANSCEIVER
static void hdsl_i2c_io_expander(void *args);
#endif
uint32_t read_encoder_resolution(HDSL_Handle hdslHandle);
#if !defined(HDSL_MULTI_CHANNEL) && defined(_DEBUG_)
void App_udmaEventCb(Udma_EventHandle eventHandle, uint32_t eventType, void *appData);
static void App_udmaTrpdInit(Udma_ChHandle chHandle,
uint8_t *trpdMem,
const void *destBuf,
const void *srcBuf,
uint32_t length);
void udma_copy(uint8_t *srcBuf, uint8_t *destBuf, uint32_t length);
static void HDSL_IsrFxn();
void traces_into_memory(HDSL_Handle hdslHandle);
#endif
/* ========================================================================== */
/* Global Variables */
/* ========================================================================== */
@ -244,6 +255,7 @@ uint8_t gUdmaTestTrpdMem[UDMA_TEST_TRPD_SIZE] __attribute__((aligned(UDMA_CACHEL
/* Function Definitions */
/* ========================================================================== */
#if !defined(HDSL_MULTI_CHANNEL) && defined(_DEBUG_)
static void App_udmaTrpdInit(Udma_ChHandle chHandle,
uint8_t *trpdMem,
@ -408,11 +420,11 @@ void sync_calculation(HDSL_Handle hdslHandle)
uint32_t counter, period, index;
volatile uint32_t cap6_rise0, cap6_rise1, cap6_fall0, cap6_fall1;
uint8_t EXTRA_EDGE_ARR[8] = {0x00 ,0x80, 0xC0, 0xE0, 0xF0, 0xF8, 0xFC, 0xFE};
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000)
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==PRU_CLK_FREQ_225M)
uint32_t minm_bits = 112, cycle_per_bit = 24, max_stuffing = 26, stuffing_size = 6, cycle_per_overclock_bit =3, minm_extra_size = 4, sync_param_mem_start = 0xDC;
uint32_t cycles_left, additional_bits, minm_cycles, time_gRest, extra_edge, extra_size, num_of_stuffing, extra_size_remainder, stuffing_remainder, bottom_up_cycles;
#endif
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000)
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==PRU_CLK_FREQ_300M)
uint32_t minm_bits = 112, cycle_per_bit = 32, max_stuffing = 26, stuffing_size = 6, cycle_per_overclock_bit =4, minm_extra_size = 4, sync_param_mem_start = 0xDC;
uint32_t cycles_left, additional_bits, minm_cycles, time_gRest, extra_edge, extra_size, num_of_stuffing, extra_size_remainder, stuffing_remainder, bottom_up_cycles;
#endif
@ -445,7 +457,6 @@ void sync_calculation(HDSL_Handle hdslHandle)
period = cap6_rise1 - cap6_rise0;
/*measure of SYNC period ends*/
minm_cycles = minm_bits * ES * cycle_per_bit;
cycles_left = period - minm_cycles;
time_gRest = (cycles_left % cycle_per_bit) / cycle_per_overclock_bit;
@ -471,7 +482,7 @@ void sync_calculation(HDSL_Handle hdslHandle)
{
wait_before_start = wait_before_start+(stuffing_size * cycle_per_bit);
}
wait_before_start = wait_before_start - 51;
wait_before_start=wait_before_start+SYNC_PULSE_WAIT_CLK_CYCLES;
if(extra_size < 4 || extra_size > 9)
{
DebugP_log("\r\n ERROR: ES or period selected is Invalid ");
@ -489,10 +500,10 @@ void sync_calculation(HDSL_Handle hdslHandle)
DebugP_log("\r\n SYNC MODE: extra_size_remainder = %d", extra_size_remainder);
DebugP_log("\r\n SYNC MODE: stuffing_remainder = %d", stuffing_remainder);
DebugP_log("\r\n ********************************************************************");
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000)
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==PRU_CLK_FREQ_225M)
sync_param_mem_start =sync_param_mem_start + (uint32_t)gPru_dramx;
#endif
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000)
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==PRU_CLK_FREQ_300M)
sync_param_mem_start =sync_param_mem_start + (uint32_t)hdslHandle->baseMemAddr;
#endif
HWREGB(sync_param_mem_start) = extra_size;
@ -730,7 +741,7 @@ void hdsl_pruss_init_300m(void)
void hdsl_pruss_load_run_fw(HDSL_Handle hdslHandle)
{
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000)
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==PRU_CLK_FREQ_225M)
PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_PRUx);
if(HDSL_get_sync_ctrl(hdslHandle) == 0)
{
@ -754,7 +765,7 @@ void hdsl_pruss_load_run_fw(HDSL_Handle hdslHandle)
void hdsl_pruss_load_run_fw_300m(HDSL_Handle hdslHandle)
{
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000)
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==PRU_CLK_FREQ_300M)
PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_RTU_PRU1); // ch0
PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_PRU1); // ch1
@ -877,8 +888,26 @@ void hdsl_init_300m(void)
if(ES != 0)
{
DebugP_log("\r\nSYNC MODE\n");
DebugP_log("\r\nEnter period for SYNC PULSE in unit of cycles(1 cycle = 3.33ns):");
DebugP_log("\r\nEnter ES and period for SYNC PULSE in unit of cycles(1 cycle = 3.33ns):");
DebugP_scanf("%d",&ES);
HDSL_set_sync_ctrl(gHdslHandleCh0,ES);
HDSL_set_sync_ctrl(gHdslHandleCh1,ES);
DebugP_scanf("%d",&period);
/* Check Sync period condition
(Tsync= Cycle time for input SYNC pulse signal ,
Tmin=MIN_SYNC_CYCLE_TIME, Tmax=MAX_SYNC_CYCLE_TIME
Tsync=period/(PRU clock freq) = period/300)
ES <= Tsync/Tmin and ES >= Tsync/Tmax */
if ((ES > (period/(MIN_SYNC_CYCLE_TIME*300))) || (ES < (period/(MAX_SYNC_CYCLE_TIME*300))))
{
DebugP_log("\r\n FAIL: HDSL ES or period value you entered is not valid");
while(1)
;
}
HDSL_enable_sync_signal(ES,period);
if (CONFIG_HDSL0_CHANNEL0==1)
{
@ -1387,7 +1416,7 @@ void hdsl_diagnostic_main(void *arg)
gPruIcss0Handle = PRUICSS_open(CONFIG_PRU_ICSS0);
// initialize hdsl handle
DebugP_log( "\n\n Hiperface DSL diagnostic\n");
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000)
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==PRU_CLK_FREQ_225M)
gHdslHandleCh0 = HDSL_open(gPruIcss0Handle, PRUICSS_PRUx,0);
hdsl_init();
hdsl_pruss_load_run_fw(gHdslHandleCh0);

7
source/position_sense/hdsl/firmware/datalink.asm
View File

@ -2177,9 +2177,12 @@ send_header_extra_not_too_small1:
qbge extra_size_validation_done1, REG_TMP0.b0, 9 ;too large extra window
sub EXTRA_SIZE_COMP, EXTRA_SIZE_COMP, 6
add NUM_STUFFING_COMP, NUM_STUFFING_COMP, 1
extra_size_validation_done1:
num_pulses_is_not_one2:
jmp extra_size_validation_done1
num_pulses_is_not_one2:
loop extra_size_validation_done1,2
PUSH_FIFO_2B_8x
extra_size_validation_done1:
.if !$defined("HDSL_MULTICHANNEL")
jmp comp_logic_done_1
.endif

2
source/position_sense/hdsl/firmware/defines.inc
View File

@ -34,7 +34,7 @@
; bit7..4 major number
FIRMWARE_VERSION_MAJOR .set 0x0
; bit3..0 minor number
FIRMWARE_VERSION_MINOR .set 0x9
FIRMWARE_VERSION_MINOR .set 0xA
ICSS_FIRMWARE_RELEASE .set ((FIRMWARE_VERSION_MAJOR << 4) | (FIRMWARE_VERSION_MINOR << 0))

3
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h
View File

@ -51,6 +51,7 @@
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x21078000,
0x2eff8f8e,
@ -1650,7 +1651,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x81080580,
0x240003c0,
0x810605c0,
0x24000900,
0x24000a00,
0x810b1800,
0x81441800,
0x2eff8383,

59
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h
View File

@ -51,8 +51,9 @@
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x2107c400,
0x2107d400,
0x2eff8f8e,
0x24000725,
0x24041e8d,
@ -115,7 +116,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x23034bd1,
0x1d03c4c4,
0x2302ddd1,
0x2306119d,
0x2306219d,
0x05014545,
0x51074514,
0x49004502,
@ -573,14 +574,14 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0xd703ffff,
0x2400001e,
0x2400ff1e,
0x21041100,
0x21042100,
0x69074507,
0xc901c405,
0xd104ff00,
0xd703ffff,
0x2400ff1e,
0x2400ff1e,
0x21046500,
0x21047500,
0x51000c4a,
0x51015b04,
0x100c0c02,
@ -703,7 +704,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x79000002,
0x2400ff1e,
0x09017979,
0x21058400,
0x21059400,
0xd1077905,
0xd104ff00,
0xd703ffff,
@ -760,7 +761,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x106d6d79,
0x2400027b,
0x21037800,
0x2104af00,
0x2104bf00,
0xd104ff00,
0xd703ffff,
0xd1074d03,
@ -893,7 +894,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x91a91800,
0x01010000,
0x81a91800,
0x2106a400,
0x2106b400,
0x20d10000,
0x117f6666,
0xc9066604,
@ -940,7 +941,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x48100002,
0x10000010,
0x20d10000,
0x69015b6f,
0x69015b70,
0xd1077905,
0xd104ff00,
0xd703ffff,
@ -1048,15 +1049,31 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x59040003,
0x01062a2a,
0x05016a6a,
0x71090003,
0x71090013,
0x05062a2a,
0x01016a6a,
0x2103f700,
0x3101000f,
0xd1077905,
0xd104ff00,
0xd703ffff,
0x2400001e,
0x79000004,
0xd104ff00,
0xd703ffff,
0x2400ff1e,
0x09017979,
0xd1077903,
0x2400001e,
0x79000002,
0x2400ff1e,
0x09017979,
0x51027b06,
0x51037b03,
0x2400017b,
0x2102c500,
0x2400017b,
0x2104af00,
0x2104bf00,
0xd104ff00,
0xd703ffff,
0xd1077903,
@ -1084,7 +1101,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x2400ff1e,
0x09017979,
0x2400017b,
0x2104af00,
0x2104bf00,
0x2eff838e,
0x24003f00,
0x81401800,
@ -1146,7 +1163,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x686e5303,
0x24000019,
0x79000002,
0x230684d1,
0x230694d1,
0x10535300,
0x10333320,
0x10131340,
@ -1158,7 +1175,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x815618c4,
0x815818d8,
0x81637894,
0x21045800,
0x21046800,
0x31010004,
0xd104ff00,
0xd703ffff,
@ -1353,7 +1370,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x24003001,
0xd1066b0e,
0x2400010d,
0x2307b6d1,
0x2307c6d1,
0x68ab8d45,
0x13803b3b,
0x913d1880,
@ -1366,7 +1383,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x81531800,
0x7900003b,
0x2400020d,
0x2307b6d1,
0x2307c6d1,
0x688b8d38,
0x8137184b,
0x13803b3b,
@ -1409,7 +1426,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x1d09c4c4,
0x2400040d,
0x24003001,
0x2307b6d1,
0x2307c6d1,
0x15ff8d9c,
0x69005c34,
0x51009c33,
@ -1652,7 +1669,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0xd703ffff,
0x2400001e,
0x2400001e,
0x23066bd1,
0x23067bd1,
0x108b8b9d,
0x91aa1800,
0x1f018000,
@ -1676,7 +1693,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0xd703ffff,
0x2400001e,
0x2400001e,
0x23066bd1,
0x23067bd1,
0x91983880,
0x10eeeee1,
0x24000061,
@ -1766,11 +1783,11 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x81080580,
0x240003c0,
0x810605c0,
0x24000900,
0x24000a00,
0x810b1800,
0x81441800,
0x2eff8383,
0x2304099d,
0x2304199d,
0x24000866,
0x2400000c,
0x2400002c,
@ -2043,5 +2060,5 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x91003c82,
0x1308e2e2,
0x81003c82,
0x2106a400};
0x2106b400};

3
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h
View File

@ -51,6 +51,7 @@
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x21078100,
0x2eff8f8e,
@ -1651,7 +1652,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x81100580,
0x240003c0,
0x810605c0,
0x24000900,
0x24000a00,
0x810b1800,
0x81441800,
0x2eff8383,

59
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h
View File

@ -51,8 +51,9 @@
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x2107c500,
0x2107d500,
0x2eff8f8e,
0x24000725,
0x24041e8d,
@ -115,7 +116,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x23034bd1,
0x1d03c4c4,
0x2302ddd1,
0x2306119d,
0x2306219d,
0x05014545,
0x51074514,
0x49004502,
@ -573,14 +574,14 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0xd70bffff,
0x2400001e,
0x2400ff1e,
0x21041100,
0x21042100,
0x69074507,
0xc901c405,
0xd10cff00,
0xd70bffff,
0x2400ff1e,
0x2400ff1e,
0x21046500,
0x21047500,
0x51000c4a,
0x51015b04,
0x100c0c02,
@ -703,7 +704,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x79000002,
0x2400ff1e,
0x09017979,
0x21058400,
0x21059400,
0xd1077905,
0xd10cff00,
0xd70bffff,
@ -760,7 +761,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x106d6d79,
0x2400027b,
0x21037800,
0x2104af00,
0x2104bf00,
0xd10cff00,
0xd70bffff,
0xd1074d03,
@ -893,7 +894,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x91a91800,
0x01010000,
0x81a91800,
0x2106a400,
0x2106b400,
0x20d10000,
0x117f6666,
0xc9066604,
@ -940,7 +941,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x48100002,
0x10000010,
0x20d10000,
0x69015b6f,
0x69015b70,
0xd1077905,
0xd10cff00,
0xd70bffff,
@ -1048,15 +1049,31 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x59040003,
0x01062a2a,
0x05016a6a,
0x71090003,
0x71090013,
0x05062a2a,
0x01016a6a,
0x2103f700,
0x3101000f,
0xd1077905,
0xd10cff00,
0xd70bffff,
0x2400001e,
0x79000004,
0xd10cff00,
0xd70bffff,
0x2400ff1e,
0x09017979,
0xd1077903,
0x2400001e,
0x79000002,
0x2400ff1e,
0x09017979,
0x51027b06,
0x51037b03,
0x2400017b,
0x2102c500,
0x2400017b,
0x2104af00,
0x2104bf00,
0xd10cff00,
0xd70bffff,
0xd1077903,
@ -1084,7 +1101,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x2400ff1e,
0x09017979,
0x2400017b,
0x2104af00,
0x2104bf00,
0x2eff838e,
0x24003f00,
0x81401800,
@ -1146,7 +1163,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x686e5303,
0x24000019,
0x79000002,
0x230684d1,
0x230694d1,
0x10535300,
0x10333320,
0x10131340,
@ -1158,7 +1175,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x815618c4,
0x815818d8,
0x81637894,
0x21045800,
0x21046800,
0x31010004,
0xd10cff00,
0xd70bffff,
@ -1353,7 +1370,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x24003001,
0xd1066b0e,
0x2400010d,
0x2307b7d1,
0x2307c7d1,
0x68ab8d45,
0x13803b3b,
0x913d1880,
@ -1366,7 +1383,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x81531800,
0x7900003b,
0x2400020d,
0x2307b7d1,
0x2307c7d1,
0x688b8d38,
0x8137184b,
0x13803b3b,
@ -1409,7 +1426,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x1d09c4c4,
0x2400040d,
0x24003001,
0x2307b7d1,
0x2307c7d1,
0x15ff8d9c,
0x69005c34,
0x51009c33,
@ -1652,7 +1669,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0xd70bffff,
0x2400001e,
0x2400001e,
0x23066bd1,
0x23067bd1,
0x108b8b9d,
0x91aa1800,
0x1f018000,
@ -1676,7 +1693,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0xd70bffff,
0x2400001e,
0x2400001e,
0x23066bd1,
0x23067bd1,
0x91983880,
0x10eeeee1,
0x24000061,
@ -1767,11 +1784,11 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x81100580,
0x240003c0,
0x810605c0,
0x24000900,
0x24000a00,
0x810b1800,
0x81441800,
0x2eff8383,
0x2304099d,
0x2304199d,
0x24000866,
0x2400000c,
0x2400002c,
@ -2044,5 +2061,5 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x91003c82,
0x1308e2e2,
0x81003c82,
0x2106a400};
0x2106b400};