Pull request #125: am243x: docs: Update bug list in release notes

Merge in PINDSW/motor_control_sdk from PINDSW-7480_update_buglist to next

* commit '1b3a75198931186068a5a3471d62596225db9295':
  am243x: docs: Update bug list in release notes

docs_src/docs/api_guide/components/position_sense/hdsl.md

@@ -25,6 +25,8 @@ The HDSL firmware running on ICSS-PRU provides a defined well interface to execu
 	- Two channel support on am243x-lp
 - Tested with three different encoder makes (EDM35, EKS36, EKM36)
 
+\note Channel 2 can be enabled only if channel 0 is enabled because of code overlay scheme needed in TX-PRU. See \ref HDSL_DESIGN_TXPRU_OVERLAY for more details
+
 ## Features Not Supported
 
 In general, peripherals or features not mentioned as part of "Features Supported" section are not

docs_src/docs/api_guide/components/position_sense/hdsl_design.md

@@ -32,7 +32,7 @@ Figure "Layer Model" illustrates the relationship between the two layers.
 
 \image html hdsl_layer_model.png "Layer Model"
 
-### Overlay Scheme for TX-PRU
+### Overlay Scheme for TX-PRU {#HDSL_DESIGN_TXPRU_OVERLAY}
 
 Each PRU-ICSSG has two slices, and each slice has three cores : PRU, RTU-PRU and TX-PRU. The instruction memory for PRU, RTU-PRU and TX-PRU coreS is 12 kB, 8 kB and 6 kB respctively. Multi-channel implementation of Hiperface DSL is achieved by enabling load share mode of PRU-ICSSG where one core is responsible for one channel. One PRU-ICSSG slice supports three peripheral interfaces for HDSL. Mapping is fixed to channel 0 with RTU-PRU, channel 1 with TX-PRU. To implement an equivalent data link layer and transport layer as the reference IP-core for the Hiperface DSL on FPGA, the instruction memory for TX-PRU is not enough. Hence a code overlay scheme is required only for TX-PRU core, which is only needed if channel 2 is enabled.
 

docs_src/docs/api_guide/device/am243x/release_notes_09_01_00.md

@@ -184,6 +184,20 @@ Below features are not support on AM243X LAUNCHPAD due to SOC or board constrain
     <td> 9.0
     <td> QM updates for Safe Channel 2 were incorrect.
 </tr>
+<tr>
+    <td> PINDSW-6973
+    <td> Flash addition in SysConfig of Industrial Communications and Motor control SDK fails to load flashconfig.json due to error in file path
+    <td> Motor Control SDK
+    <td> 9.0
+    <td> -
+</tr>
+<tr>
+    <td> PINDSW-6977
+    <td> Unable to build the examples of Industrial Communications SDK inside Motor Control SDK
+    <td> Motor Control SDK
+    <td> 9.0
+    <td> -
+</tr>
 <tr>
     <td> PINDSW-7048
     <td> HDSL: SCE bit in ONLINE STATUS 1 gets cleared before seeing a correct CRC in safe channel
@@ -191,6 +205,20 @@ Below features are not support on AM243X LAUNCHPAD due to SOC or board constrain
     <td> 9.0
     <td> -
 </tr>
+<tr>
+    <td> PINDSW-7115
+    <td> Gmake based command for PRU empty project build fails in Motor Control SDK and Industrial Communications SDK
+    <td> Motor Control SDK
+    <td> 9.0
+    <td> -
+</tr>
+<tr>
+    <td> PINDSW-7125
+    <td> EnDat: Initialization is failing for multi-channel single pru example with LP
+    <td> Position Sense EnDat
+    <td> 9.0
+    <td> -
+</tr>
 <tr>
     <td> PINDSW-7126
     <td> HDSL: Protocol reset is seen multiple times with certain encoders
@@ -212,6 +240,13 @@ Below features are not support on AM243X LAUNCHPAD due to SOC or board constrain
     <td> 9.0
     <td> -
 </tr>
+<tr>
+    <td> PINDSW-7467
+    <td> Industrial Communications SDK modules are not visible in the SysConfig of Motor Control SDK
+    <td> Motor Control SDK
+    <td> 9.0
+    <td> -
+</tr>
 <tr>
     <td> PINDSW-7473
     <td> HDSL : 100 meter cable length does not work for Free Run mode in 300Mhz PRU clock
@@ -294,6 +329,13 @@ Below features are not support on AM243X LAUNCHPAD due to SOC or board constrain
     <td> 9.0
     <td> -
 </tr>
+<tr>
+    <td> PINDSW-7480
+    <td> HDSL: Continuous short/long message requests cause PRU to get stuck
+    <td> Position Sense HDSL
+    <td> 9.0
+    <td> -
+</tr>
 </table>
 
 <!-- ## Errata

docs_src/docs/api_guide/examples/hdsl_example.md

@@ -16,11 +16,14 @@ It then presents the user with menu options, based on the option selected, appli
 
 This example also allows the capability to save the HDSL register data into memory for the defined duration.
 
+
 \cond SOC_AM243X
 - For @VAR_BOARD_NAME_LOWER example, the data is stored in DDR.
 - For @VAR_LP_BOARD_NAME_LOWER example, the data is stored in MSRAM.
 \endcond
 
+\note Channel 2 can be enabled only if channel 0 is enabled because of code overlay scheme needed in TX-PRU. See \ref HDSL_DESIGN_TXPRU_OVERLAY for more details
+
 \note The HDSL register trace option is only available with debug mode builds for single channel examples.
 
 ## Important files and directory structure