From 7605041284ded7ea98f98980967b2102a1921af4 Mon Sep 17 00:00:00 2001
From: Dhaval Khandla <dhavaljk@ti.com>
Date: Tue, 22 Aug 2023 11:52:20 +0530
Subject: [PATCH] am64x/am243x: hdsl: Fix the SUM/SSUM/FIX1 bit configuration
 in ONLINE STATUS registers

- MASK_SUM should not be used for masking SUMMARY while updating these
  SUM and SSUM bits in ONLINE STATUS registers
- Fix the mask for SCE and VPOS updates

Fixes: PINDSW-6487, PINDSW-6488

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
---
 .../firmware/hdsl_master_icssg_300_mhz_bin.h  | 52 ++++++++++---------
 .../hdsl/firmware/transport.asm               | 15 ++++--
 2 files changed, 37 insertions(+), 30 deletions(-)

diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h
index d15aad9..cd21d72 100644
--- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h
+++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h
@@ -55,7 +55,7 @@
  */
 
 const unsigned int Hiperface_DSL2_0[]= {
-0x21067800,
+0x21067a00,
 0x24000125,
 0x2eff818f,
 0x24001d8d,
@@ -151,7 +151,7 @@ const unsigned int Hiperface_DSL2_0[]= {
 0xd104ff00,
 0xd703ffff,
 0x24002f1e,
-0x23046a9d,
+0x23046c9d,
 0x05014545,
 0x4f0045d2,
 0x24000070,
@@ -523,14 +523,14 @@ const unsigned int Hiperface_DSL2_0[]= {
 0x12006d6d,
 0x09064d4d,
 0xc901c402,
-0x2103db00,
+0x2103dd00,
 0xd104ff00,
 0xd703ffff,
 0x106d6d1e,
 0x511f0d03,
 0x51190d02,
 0x79000003,
-0x23063fd1,
+0x230641d1,
 0x7900001a,
 0xd104ff00,
 0xd703ffff,
@@ -542,7 +542,7 @@ const unsigned int Hiperface_DSL2_0[]= {
 0x511f0d12,
 0x51190d11,
 0xc901c402,
-0x21032000,
+0x21032200,
 0x910c3c81,
 0x240117e0,
 0x04e1e0e0,
@@ -637,7 +637,7 @@ const unsigned int Hiperface_DSL2_0[]= {
 0x1f00c0c0,
 0x1f008181,
 0x81505880,
-0x2104f500,
+0x2104f700,
 0x91042580,
 0xd708e0ff,
 0x91042580,
@@ -707,7 +707,7 @@ const unsigned int Hiperface_DSL2_0[]= {
 0x81601881,
 0xd104c40e,
 0x91521801,
-0x110b0101,
+0x11db0101,
 0x5100980c,
 0x913d1880,
 0x1f050000,
@@ -770,7 +770,7 @@ const unsigned int Hiperface_DSL2_0[]= {
 0x813a188d,
 0x24000019,
 0x79000002,
-0x2304d4d1,
+0x2304d6d1,
 0x10535300,
 0x10333320,
 0x10131340,
@@ -836,10 +836,7 @@ const unsigned int Hiperface_DSL2_0[]= {
 0x81361800,
 0x91081821,
 0x10210001,
-0x91503802,
-0x1d060202,
-0x1d060242,
-0x5100010d,
+0x5100010b,
 0x91043880,
 0x1f068080,
 0x81041880,
@@ -850,6 +847,11 @@ const unsigned int Hiperface_DSL2_0[]= {
 0x813d1880,
 0xc9062002,
 0x2400269f,
+0x91361800,
+0x91503802,
+0x1d060202,
+0x1d060242,
+0x51000003,
 0x1f060202,
 0x1f060242,
 0x81503802,
@@ -931,7 +933,7 @@ const unsigned int Hiperface_DSL2_0[]= {
 0x24003001,
 0xd1066b0e,
 0x2400010d,
-0x23066ad1,
+0x23066cd1,
 0x68ab8d45,
 0x13803b3b,
 0x913d1880,
@@ -944,7 +946,7 @@ const unsigned int Hiperface_DSL2_0[]= {
 0x81531800,
 0x7900003b,
 0x2400020d,
-0x23066ad1,
+0x23066cd1,
 0x688b8d38,
 0x8137184b,
 0x13803b3b,
@@ -987,7 +989,7 @@ const unsigned int Hiperface_DSL2_0[]= {
 0x1d09c4c4,
 0x2400040d,
 0x24003001,
-0x23066ad1,
+0x23066cd1,
 0x15ff8d9c,
 0x69005c34,
 0x51009c33,
@@ -1228,7 +1230,7 @@ const unsigned int Hiperface_DSL2_0[]= {
 0x108787c7,
 0x04c98087,
 0x108080c9,
-0x2304bbd1,
+0x2304bdd1,
 0x108b8b9d,
 0x91aa1800,
 0x1f018000,
@@ -1248,7 +1250,7 @@ const unsigned int Hiperface_DSL2_0[]= {
 0x108787c7,
 0x04c98087,
 0x108080c9,
-0x2304bbd1,
+0x2304bdd1,
 0x91983880,
 0x10eeeee1,
 0x24000061,
@@ -1368,7 +1370,7 @@ const unsigned int Hiperface_DSL2_0[]= {
 0x9101185b,
 0x51005b0e,
 0x7900000d,
-0x230627d1,
+0x230629d1,
 0x91dc388c,
 0x240000e2,
 0x91e21882,
@@ -1376,7 +1378,7 @@ const unsigned int Hiperface_DSL2_0[]= {
 0x100c0c2a,
 0x106c6c4a,
 0x102c2c6a,
-0x230627d1,
+0x230629d1,
 0x0b01e2e2,
 0x0501e2e2,
 0x4f00e2ff,
@@ -1499,7 +1501,7 @@ const unsigned int Hiperface_DSL2_0[]= {
 0x0b077200,
 0x12001313,
 0x0901f2f2,
-0x230633d1,
+0x230635d1,
 0x510e6506,
 0x6f010df6,
 0x10656546,
@@ -1538,16 +1540,16 @@ const unsigned int Hiperface_DSL2_0[]= {
 0xd703ffff,
 0x24001b8d,
 0x23016a9d,
-0x2305f99d,
-0x230633d1,
+0x2305fb9d,
+0x230635d1,
 0x6f010dea,
 0x05012525,
 0x4f0025f8,
 0x24001025,
 0x24001c8d,
 0x23016a9d,
-0x2305f99d,
-0x230633d1,
+0x2305fb9d,
+0x230635d1,
 0x6f010dd6,
 0x05012525,
 0x4f0025fa,
@@ -1714,4 +1716,4 @@ const unsigned int Hiperface_DSL2_0[]= {
 0x91003c82,
 0x1308e2e2,
 0x81003c82,
-0x2104f400 };
+0x2104f600 };
diff --git a/source/position_sense/hdsl/firmware/transport.asm b/source/position_sense/hdsl/firmware/transport.asm
index 3ef3f10..e429f11 100644
--- a/source/position_sense/hdsl/firmware/transport.asm
+++ b/source/position_sense/hdsl/firmware/transport.asm
@@ -112,7 +112,7 @@ transport_on_v_frame:
 ;transmission error?
 	qbbs		transport_on_v_frame_dont_update_qm, H_FRAME.flags, FLAG_ERR_VERT
     lbco		&REG_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
-    and         REG_TMP1.b0, REG_TMP1.b0, (~((1<<ONLINE_STATUS_1_SCE) | (1<<ONLINE_STATUS_1_VPOS)) & 0xF)
+    and         REG_TMP1.b0, REG_TMP1.b0, (~((1<<ONLINE_STATUS_1_SCE) | (1<<ONLINE_STATUS_1_VPOS)) & 0xFF)
 ;checking for crc error
 	qbeq		check_for_slave_error_on_v_frame, CRC_VERT, 0
 ; Set EVENT_S_SCE in EVENT register
@@ -366,9 +366,6 @@ transport_skip_vpos_update:
 ;check SUMMARY and MASK_SUM
     lbco		&REG_TMP1.b1, MASTER_REGS_CONST, MASK_SUM, 1
 	and		    REG_TMP1.b0, REG_TMP0.b0, REG_TMP1.b1
-	lbco		&REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 3
-    clr         REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM
-    clr         REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM
 	qbeq		summary_no_int, REG_TMP1.b0, 0x00
 ;set event and generate interrupt
 	lbco		&REG_TMP0, MASTER_REGS_CONST, EVENT_H, 4
@@ -389,9 +386,17 @@ update_events_no_int7:
 ; generate interrupt_s
 	ldi		r31.w0, PRU0_ARM_IRQ4
 update_events_no_int17:
+summary_no_int:
+
+; Update SUM and SSUM bits in ONLINE_STATUS registers
+    lbco		&REG_TMP0.b0, MASTER_REGS_CONST, SAFE_SUM, 1
+	lbco		&REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 3
+    clr         REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM
+    clr         REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM
+	qbeq		online_status_sum_clear, REG_TMP0.b0, 0x00
     set         REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_D_SUM
     set         REG_TMP2.b2, REG_TMP2.b0, ONLINE_STATUS_1_SSUM
-summary_no_int:
+online_status_sum_clear:
     sbco		&REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 3
 
 ;restore REG_FNC.w0 content