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Pull request #122: am243x: hdsl: Update the linker to define alignment of copy table

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Merge in PINDSW/motor_control_sdk from PINDSW-7051_fix_linker_for_freerun to next

* commit '0fb9cd68d1a238da6a64dcbaa4c47caea9625b76':
  am243x: hdsl: Update the linker to define alignment of copy table
This commit is contained in:
Dhaval Khandla 2024-01-08 22:33:54 -06:00 committed by Jayachandran (JC)
commit 6439bb04c8
6 changed files with 12 additions and 6 deletions
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3
examples/position_sense/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
View File

@ -110,7 +110,8 @@ SECTIONS
As this array is typecasted into a structure with 32-bit variables,
32b alignment is required
*/
.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM
.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2 : {} align(32) > MSRAM
.rodata.Hiperface_DSL2_0_TX_PRU_2 : {} align(32) > MSRAM
}
/*

3
examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
View File

@ -110,7 +110,8 @@ SECTIONS
As this array is typecasted into a structure with 32-bit variables,
32b alignment is required
*/
.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM
.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2 : {} align(32) > MSRAM
.rodata.Hiperface_DSL2_0_TX_PRU_2 : {} align(32) > MSRAM
}
/*

3
examples/position_sense/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
View File

@ -110,7 +110,8 @@ SECTIONS
As this array is typecasted into a structure with 32-bit variables,
32b alignment is required
*/
.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM
.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2 : {} align(32) > MSRAM
.rodata.Hiperface_DSL2_0_TX_PRU_2 : {} align(32) > MSRAM
}
/*

3
examples/position_sense/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
View File

@ -112,7 +112,8 @@ SECTIONS
As this array is typecasted into a structure with 32-bit variables,
32b alignment is required
*/
.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM
.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2 : {} align(32) > MSRAM
.rodata.Hiperface_DSL2_0_TX_PRU_2 : {} align(32) > MSRAM
}
/*

3
examples/position_sense/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
View File

@ -112,7 +112,8 @@ SECTIONS
As this array is typecasted into a structure with 32-bit variables,
32b alignment is required
*/
.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM
.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2 : {} align(32) > MSRAM
.rodata.Hiperface_DSL2_0_TX_PRU_2 : {} align(32) > MSRAM
}
/*

3
examples/position_sense/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
View File

@ -112,7 +112,8 @@ SECTIONS
As this array is typecasted into a structure with 32-bit variables,
32b alignment is required
*/
.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM
.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2 : {} align(32) > MSRAM
.rodata.Hiperface_DSL2_0_TX_PRU_2 : {} align(32) > MSRAM
}
/*