diff --git a/docs_src/docs/api_guide/components/current_sense/current_sense.md b/docs_src/docs/api_guide/components/current_sense/current_sense.md
index 164040d..75dd5ea 100644
--- a/docs_src/docs/api_guide/components/current_sense/current_sense.md
+++ b/docs_src/docs/api_guide/components/current_sense/current_sense.md
@@ -13,16 +13,22 @@ ICSS %SDFM is a sigma delta interface for phase current measurement in high perf
  - Normal current (NC) for data read:  SINC3 filter with OSR 16 to 256
  - Overcurrent (OC) for comparator: free running SINC3 filter with OSR 16 to 256
  - Event generation(ARM interrupt for data read from DMEM, GPIO toggle for high and low thresholds)
- - High and Low threshold comparator
+ - Single level High and Low threshold comparator
  - Trigger based normal current sampling
  - Double update: Double normal current sampling per EPWM cycle 
  - %SDFM Sync with EPWM 
+ - Fast detect 
+ - PWM Trip generation for overcurrent 
 
 ## Features Not Supported
 - Zero cross comparator
-- OSR below 16
 - Clock phase compensation 
-- Fast detect and trip generation
+- Multi-level threshold 
+
+## System design considerations
+### Over Sample Ratio 
+-  OSR Below 16 at SD_CLK greater than 20MHz. The normal current task takes 300ns to 400ns to complete and its execution is based on CMP event and task manager. When we configure OSR below 16 for greater than 20 MHz SD clock, the NC will not be able to complete its processing until the next sample is ready, this will cause the NC samples to be inaccurate.
+     
 
 ## ICSS SDFM Design
 \subpage SDFM_DESIGN explains the design in detail.
diff --git a/docs_src/docs/api_guide/components/current_sense/sdfm_design.md b/docs_src/docs/api_guide/components/current_sense/sdfm_design.md
index 937e247..314cb9a 100644
--- a/docs_src/docs/api_guide/components/current_sense/sdfm_design.md
+++ b/docs_src/docs/api_guide/components/current_sense/sdfm_design.md
@@ -103,6 +103,10 @@ The firmware initiates normal current sampling at the sample trigger point in ea
 Here ONE_SAMPLE_TIME is: OSR*(1/SD_CLK)  
 \image html SDFM_epwm_sync_and_trigger_timing.png "Sync with EPWM and trigger timing"
 
+#### Fast Detect and Trip generation
+The Fast Detect block is used for fast over current detection, it comparatively measures the number of zeros and ones presented in a programmable sliding window of 4 to 32 bits. It starts the comparison after the first 32 sample clocks. Based on the configured zero max/min count limits, it compares zero counter with these limits. If zero counter crosses limit then it sends a error signal to respective PWM Trip zone block.
+PWM TZ block receives this error signal and generates a Trip on TZ_OUT pin.
+
 #### AM64x/AM243x EVM Pin-Multiplexing
 <table>
 <tr>
@@ -235,5 +239,10 @@ Here ONE_SAMPLE_TIME is: OSR*(1/SD_CLK)
     <td>PIN_PRG0_PRU0_GPO16
 	<td>(J1.7)Comman %SDFM clock input pin
 </tr>
+<tr>
+    <td>PWM0_TZ_OUT
+    <td>PIN_PRG0_PRU0_GPO19
+	<td>(J5.45)TZ output pin for Axis-1
+</tr>
 </table>
 \endcond
\ No newline at end of file
diff --git a/docs_src/docs/api_guide/examples/sdfm_example.md b/docs_src/docs/api_guide/examples/sdfm_example.md
index 26bfa81..b18c9b0 100644
--- a/docs_src/docs/api_guide/examples/sdfm_example.md
+++ b/docs_src/docs/api_guide/examples/sdfm_example.md
@@ -15,6 +15,8 @@ The ICSS %SDFM example invokes these APIs to
 - Enable & disable double update
 - Inform firmware to enable %SDFM mode
 - Configure GPIO pins for high and low threshold
+- Configure fast detect block
+
 
 
 Once these steps are executed
@@ -258,9 +260,36 @@ Other than the basic EVM setup mentioned in <a href="@VAR_MCU_SDK_DOCS_PATH/EVM_
         <td>5. Observe resolution of raw data</td>
         <td></td>
 </tr>
+<tr>
+        <td>7. To check Fast detect</td>
+        <td>1. Set NC OSR to 64</td>
+        <td> Trip must be triggered for the respective  pwm trip zone block </td>
+</tr>
+<tr>
+        <td></td>
+        <td>2. Enable Fast detect</td>
+        <td></td>
+ </tr>
+<tr>
+        <td></td>
+        <td>3. Set Fast Detect fields with these values { window size = 4, Zero max = 18, Zero min = 2}</td>
+        <td>Zero max/min Threshold hit bits must be constantly unset and set </td>
+ </tr>
+
+<tr>
+        <td></td>
+        <td>4. Build and run example</td>
+        <td>One max/min threshold hit bits must be unset</td>
+</tr>
+<tr>
+        <td></td>
+        <td>5. 1) Observe TZ_OUT PIN. 
+               2) Check zero/one count max & zero/one count min threshold hit bits in memory map</td>
+        <td></td>
+</tr>
 \cond SOC_AM243X
 <tr>
-        <td>7.Testing with sdfm clock from EPWM </td>
+        <td>8.Testing with sdfm clock from EPWM </td>
         <td>1. Make hardware set up like attached image </td>
         <td>All test cases results should match with ECAP test case results</td>
  </tr>
diff --git a/examples/current_sense/icss_sdfm/app_sdfm.c b/examples/current_sense/icss_sdfm/app_sdfm.c
index 628559e..c575e08 100644
--- a/examples/current_sense/icss_sdfm/app_sdfm.c
+++ b/examples/current_sense/icss_sdfm/app_sdfm.c
@@ -156,10 +156,15 @@ SdfmPrms gTestSdfmPrms = {
     {{0,0},                /*clock sourse & clock inversion for all channels*/
     {0,0},
     {0,0}},
-     15,   /*Over current osr: The effect count is OSR + 1*/
-     128,   /*Normal current osr */
-     1,   /*comparator enable*/
-     (uint32_t)&gSdfm_sampleOutput /*Output samples base address*/
+    15,   /*Over current osr: The effect count is OSR + 1*/
+    128,   /*Normal current osr */
+    1,   /*comparator enable*/
+    (uint32_t)&gSdfm_sampleOutput, /*Output samples base address*/
+    1,
+    {{4, 18, 2},
+    {4, 18, 2},
+    {4, 18, 2}
+    }   /*Fast detect fields {Window size, zero count max, zero count min}*/
 };
 
 #define PRUICSS_G_MUX_EN    ( 0x1 ) /* ICSSG_SA_MX_REG:G_MUX_EN */
@@ -400,6 +405,7 @@ void pruSdfmIrqHandler(void *args)
         sdfm_ch1_idx = 0;
         sdfm_ch2_idx = 0;
     }
+    
 
 
 }
diff --git a/examples/current_sense/icss_sdfm/cfg_pad.c b/examples/current_sense/icss_sdfm/cfg_pad.c
index e9d635b..88a0389 100644
--- a/examples/current_sense/icss_sdfm/cfg_pad.c
+++ b/examples/current_sense/icss_sdfm/cfg_pad.c
@@ -66,6 +66,13 @@ static Pinmux_PerCfg_t gPinMuxMainDomainCfgsdfm[] = {
         ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
     },
     
+    /* PWM0_TZ_OUT,
+       PRG0_PWM0_TZ_OUT, TZ_OUT,      R3, J2C:P6  */
+    {
+        PIN_PRG0_PRU0_GPO19,
+        ( PIN_MODE(3) | PIN_PULL_DISABLE )
+    },
+
     {PINMUX_END, PINMUX_END}
 };
 
diff --git a/examples/current_sense/icss_sdfm/sdfm.c b/examples/current_sense/icss_sdfm/sdfm.c
index 51f20ae..a72e1ad 100644
--- a/examples/current_sense/icss_sdfm/sdfm.c
+++ b/examples/current_sense/icss_sdfm/sdfm.c
@@ -170,7 +170,7 @@ void sdfm_configure_gpio_pin(sdfm_handle h_sdfm)
 
 }
 /* Initialize SDFM PRU FW */
-int32_t init_sdfm_pru_fw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm)
+int32_t init_sdfm_pru_fw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm, void *pruss_cfg)
 {
     sdfm_handle hSdfm;
 
@@ -194,6 +194,7 @@ int32_t init_sdfm_pru_fw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm
     uint32_t sampleOutputInterfaceGlobalAddr = CPU0_BTCM_SOCVIEW(pSdfmPrms->samplesBaseAddress);
     hSdfm->p_sdfm_interface->sampleBufferBaseAdd = sampleOutputInterfaceGlobalAddr;
     hSdfm->iep_inc = 1; /* Default IEP increment 1 */
+    hSdfm->pruss_cfg = pruss_cfg;
 
 
     uint8_t acc_filter = 0; //SINC3 filter
@@ -225,7 +226,11 @@ int32_t init_sdfm_pru_fw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm
 
         /*set threshold values */
         SDFM_setCompFilterThresholds(hSdfm, SDFM_CH, pSdfmPrms->threshold_parms[SDFM_CH]);
-        
+        if(pSdfmPrms->en_fd)
+        {
+            /*Fast detect configuration */
+            SDFM_configFastDetect(hSdfm, SDFM_CH, pSdfmPrms->fastDetect[SDFM_CH]);
+        }
         if(pSdfmPrms->en_com)
         {
             SDFM_enableComparator(hSdfm, SDFM_CH);       
@@ -236,7 +241,7 @@ int32_t init_sdfm_pru_fw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm
         }
 
     }
-
+    
     /*GPIO pin configuration for threshold measurment*/
     sdfm_configure_gpio_pin(hSdfm);
 
@@ -277,13 +282,16 @@ int32_t initPruSdfm(
     uint32_t byteLen;                   /* Total number of bytes to be written */
     uint8_t pruId;
     int32_t status;
+    void *pruss_cfg;
 
+    pruss_cfg = (void *)(((PRUICSS_HwAttrs *)(pruIcssHandle->hwAttrs))->cfgRegBase);
     /* Reset PRU */
     status = PRUICSS_resetCore(pruIcssHandle, pruInstId);
     if (status != SystemP_SUCCESS) {
         return SDFM_ERR_INIT_PRU_SDFM;
     }
 
+
     /* Calculate slice ID */
     sliceId = pruInstId - (uint8_t)pruInstId/ICSSG_NUM_SLICE * ICSSG_NUM_SLICE;
     /* Determine PRU DMEM address */
@@ -342,7 +350,7 @@ int32_t initPruSdfm(
     }
 
     /* Initialize SDFM PRU FW */
-    status = init_sdfm_pru_fw(pruId, pSdfmPrms, pHSdfm);
+    status = init_sdfm_pru_fw(pruId, pSdfmPrms, pHSdfm, pruss_cfg);
     if (status != SDFM_ERR_NERR) {
         return SDFM_ERR_INIT_PRU_SDFM;
     }
diff --git a/examples/current_sense/icss_sdfm/sdfm.h b/examples/current_sense/icss_sdfm/sdfm.h
index 1d768bc..c88e558 100644
--- a/examples/current_sense/icss_sdfm/sdfm.h
+++ b/examples/current_sense/icss_sdfm/sdfm.h
@@ -110,7 +110,7 @@
 #define ICSSG_SLICE_ID_0   ( 0 )    /* ICSSG slide ID 0 */
 #define ICSSG_SLICE_ID_1   ( 1 )    /* ICSSG slide ID 1 */
 #define ICSSG_NUM_SLICE    ( 2 )    /* ICSSG number of slices */
-
+#define NUM_FD_FIELD   ( 3 )
 /*!
  *  @brief    PRUICSS Instance IDs
  */
@@ -147,6 +147,10 @@ typedef struct SdfmPrms_s {
     uint8_t en_com;
     /**< output samples base address*/
     uint32_t samplesBaseAddress;
+    /**<enable fast detect*/
+    uint8_t en_fd;
+    /**<Fast detect configuration field*/
+    uint8_t fastDetect[NUM_SD_CH][NUM_FD_FIELD];
 } SdfmPrms;
 
 
diff --git a/source/current_sense/sdfm/driver/sdfm_drv.c b/source/current_sense/sdfm/driver/sdfm_drv.c
index dcf9eb6..fc15bc1 100644
--- a/source/current_sense/sdfm/driver/sdfm_drv.c
+++ b/source/current_sense/sdfm/driver/sdfm_drv.c
@@ -306,6 +306,43 @@ uint64_t SDFM_getFirmwareVersion(sdfm_handle h_sdfm)
 {
    return h_sdfm->p_sdfm_interface->firmwareVersion;
 }
+/*FD block confiuration */
+void SDFM_configFastDetect(sdfm_handle h_sdfm, uint8_t ch, uint8_t *fdParms)
+{
+    h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.enFastDetect |= 1<<ch;
+    h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch].fd_window = fdParms[0];
+    h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch].fd_zero_max = fdParms[1];
+    h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch].fd_zero_min = fdParms[2];
+      
+    /*Configure one max to window size + 1 and one min to 0, so they never get set*/
+    h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch].fd_one_max = (fdParms[0] + 1) * 4 + 1;
+    h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch].fd_one_min = 0;
+
+}
+
+/*return status of Trip status bit*/
+uint32_t SDFM_getPwmTripStatus(sdfm_handle h_sdfm, uint8_t pwmIns)
+{
+    void *pruss_cfg = h_sdfm->pruss_cfg;
+    uint32_t regval;
+    regval = HW_RD_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_PWM0 + pwmIns * 4);
+    regval  = regval & CSL_ICSSCFG_PWM0_PWM0_TRIP_S_MASK;
+    return regval>>CSL_ICSSCFG_PWM0_PWM0_TRIP_S_SHIFT;
+}
+
+/*Clear Trip status bit*/
+void SDFM_clearPwmTripStatus(sdfm_handle h_sdfm, uint8_t pwmIns)
+{
+    void *pruss_cfg = h_sdfm->pruss_cfg;
+    uint32_t regval;
+    regval = HW_RD_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_PWM0 + pwmIns * 4);
+    regval = regval | CSL_ICSSCFG_PWM0_PWM0_TRIP_RESET_MASK;
+    HW_WR_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_PWM0 + pwmIns * 4, regval);
+    regval = HW_RD_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_PWM0 + pwmIns * 4);
+    regval = regval & (~ CSL_ICSSCFG_PWM0_PWM0_TRIP_RESET_MASK);
+    HW_WR_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_PWM0 + pwmIns * 4, regval);
+
+}
 /* SDFM global enable */
 void SDFM_enable(sdfm_handle h_sdfm)
 {
diff --git a/source/current_sense/sdfm/firmware/icssg_sdfm.h b/source/current_sense/sdfm/firmware/icssg_sdfm.h
index 7cff31b..003fa01 100644
--- a/source/current_sense/sdfm/firmware/icssg_sdfm.h
+++ b/source/current_sense/sdfm/firmware/icssg_sdfm.h
@@ -112,6 +112,7 @@
 #define SDFM_CFG_SD_CH_ID_OFFSET             ( 0x10 )
 #define SDFM_CFG_SD_EN_COMP_OFFSET           ( 0x14 )
 #define SDFM_CFG_SD_ZC_ENABLE_OFFSET         ( 0x16 )
+#define SDFM_CFG_SD_EN_FD_OFFSET             ( 0x18 )
 
 
 /*SDFM channel offsets*/
diff --git a/source/current_sense/sdfm/firmware/sdfm.asm b/source/current_sense/sdfm/firmware/sdfm.asm
index f8de5d5..53971a9 100644
--- a/source/current_sense/sdfm/firmware/sdfm.asm
+++ b/source/current_sense/sdfm/firmware/sdfm.asm
@@ -192,9 +192,7 @@ init_sdfm_cont:
         SET     R30.t25 ; R30[25] channel_en = 1, all channels enabled
 
         ;Configure pwm TZ block
-        .if $isdefed("FD_CODE")
         JAL   RET_ADDR_REG, config_pwm_trip
-        .endif
 
         ; Initialize dedicated registers:
         ;   MASK register,
@@ -738,7 +736,8 @@ reset_sdfm_state:
 ;   SD_HW_BASE_PTR_REG: base address of SD HW configuration registers (&ICSSG_PRUn_SD_CLK_SEL_REG0)
 ;
 config_oc_osr:
-
+        ;Load fast detect enable bits
+        LBCO   &TEMP_REG3, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_SD_EN_FD_OFFSET, 1
         LDI    TEMP_REG0, 0
         ; Load TR1.w0 <- SDFM_CFG_SD_CH_ID = ;LDI      TEMP_REG1.w0, 0x210 =001100010000
         LBCO    &TEMP_REG1.w0, CT_PRU_ICSSG_LOC_DMEM,  SDFM_CFG_SD_CH_ID_OFFSET,  SDFM_CFG_SD_CH_ID_SZ
@@ -749,19 +748,18 @@ config_oc_osr:
         ; Load TR0.b0 <-  SDFM_CFG_OSR load osr from DMEM for ch0
         LBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_LOC_DMEM,  SDFM_CFG_CH0_OSR_OFFSET,  SDFM_CFG_OSR_SZ
 
-        .if $isdefed("FD_CODE")
+        QBBC   SDFM_SKIP0_CH2, TEMP_REG3.b0, 0
        ;configure fast detect one count and enable fast detect
-        LBCO   &FAST_window_REG, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_CH0_FD_WD_REG_OFFSET, 1
-        LBCO   &FAST_ONE_min_REG, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_CH0_FD_ONE_MIN_REG_OFFSET, 1
-        LBCO   &FAST_ONE_max_REG, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_CH0_FD_ONE_MAX_REG_OFFSET, 1
+        LBCO   &FAST_WINDOW_REG, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_CH0_FD_WD_REG_OFFSET, 1
+        LBCO   &FAST_ONE_MIN_REG, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_CH0_FD_ONE_MIN_REG_OFFSET, 1
+        LBCO   &FAST_ONE_MAX_REG, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_CH0_FD_ONE_MAX_REG_OFFSET, 1
 
-        MOV     TEMP_REG0.b1, FAST_window_REG
-        LSL     TEMP_REG0.b2, FAST_ONE_min_REG, 3
+        MOV     TEMP_REG0.b1, FAST_WINDOW_REG
+        LSL     TEMP_REG0.b2, FAST_ONE_MIN_REG, 3
         OR      TEMP_REG0.b1, TEMP_REG0.b2, TEMP_REG0.b1
-        LSL     TEMP_REG0.b2, FAST_ONE_max_REG, 1
+        LSL     TEMP_REG0.b2, FAST_ONE_MAX_REG, 1
         OR      TEMP_REG0.b2, TEMP_REG0.b2, 0x41;clear max & min threshold hit
         OR      TEMP_REG0.b2, TEMP_REG0.b2, 0x80;enable fast detec
-        .endif
 
         JMP    SDFM_SKIP0_CH2
 SDFM_SKIP0_CH0:
@@ -769,41 +767,42 @@ SDFM_SKIP0_CH0:
         ; Load TR0.b0 <-  SDFM_CFG_OSR load osr from DMEM for ch1
         LBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_LOC_DMEM,  SDFM_CFG_CH1_OSR_OFFSET,  SDFM_CFG_OSR_SZ
 
-         .if $isdefed("FD_CODE")
+         
+        QBBC   SDFM_SKIP0_CH2, TEMP_REG3.b0, 1
         ;configure fast detect one count and enable fast detect
-        LBCO   &FAST_window_REG, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_CH1_FD_WD_REG_OFFSET, 1
-        LBCO   &FAST_ONE_min_REG, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_CH1_FD_ONE_MIN_REG_OFFSET, 1
-        LBCO   &FAST_ONE_max_REG, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_CH1_FD_ONE_MAX_REG_OFFSET, 1
+        LBCO   &FAST_WINDOW_REG, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_CH1_FD_WD_REG_OFFSET, 1
+        LBCO   &FAST_ONE_MIN_REG, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_CH1_FD_ONE_MIN_REG_OFFSET, 1
+        LBCO   &FAST_ONE_MAX_REG, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_CH1_FD_ONE_MAX_REG_OFFSET, 1
 
-        MOV     TEMP_REG0.b1, FAST_window_REG
-        LSL     TEMP_REG0.b2, FAST_ONE_min_REG, 3
+        MOV     TEMP_REG0.b1, FAST_WINDOW_REG
+        LSL     TEMP_REG0.b2, FAST_ONE_MIN_REG, 3
         OR      TEMP_REG0.b1, TEMP_REG0.b2, TEMP_REG0.b1
-        LSL     TEMP_REG0.b2, FAST_ONE_max_REG, 1
-        OR      TEMP_REG0.b2, TEMP_REG0.b2, 0x41;clear max & min threshold hit
+        LSL     TEMP_REG0.b2, FAST_ONE_MAX_REG, 1
+        OR      TEMP_REG0.b2, TEMP_REG0.b2, 0x41;clear max & MIN threshold hit
         OR      TEMP_REG0.b2, TEMP_REG0.b2, 0x80;enable fast detect
-        .endif
+    
 
         JMP    SDFM_SKIP0_CH2
 SDFM_SKIP0_CH1:
         QBNE            SDFM_SKIP0_CH2, TEMP_REG2.b0,	SD_CH2_ID
         ; Load TR0.b0 <-  SDFM_CFG_OSR load osr from DMEM for ch2
         LBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_LOC_DMEM,  SDFM_CFG_CH2_OSR_OFFSET,  SDFM_CFG_OSR_SZ
-
-        .if $isdefed("FD_CODE")
+        
+        QBBC   SDFM_SKIP0_CH2, TEMP_REG3.b0, 2
         ;configure fast detect one count and enable fast detect
-        LBCO   &FAST_window_REG, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_CH2_FD_WD_REG_OFFSET, 1
-        LBCO   &FAST_ONE_min_REG, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_CH2_FD_ONE_MIN_REG_OFFSET, 1
-        LBCO   &FAST_ONE_max_REG, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_CH2_FD_ONE_MAX_REG_OFFSET, 1
+        LBCO   &FAST_WINDOW_REG, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_CH2_FD_WD_REG_OFFSET, 1
+        LBCO   &FAST_ONE_MIN_REG, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_CH2_FD_ONE_MIN_REG_OFFSET, 1
+        LBCO   &FAST_ONE_MAX_REG, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_CH2_FD_ONE_MAX_REG_OFFSET, 1
 
-        MOV     TEMP_REG0.b1, FAST_window_REG
-        LSL     TEMP_REG0.b2, FAST_ONE_min_REG, 3
+        MOV     TEMP_REG0.b1, FAST_WINDOW_REG
+        LSL     TEMP_REG0.b2, FAST_ONE_MIN_REG, 3
         OR      TEMP_REG0.b1, TEMP_REG0.b2, TEMP_REG0.b1
-        LSL     TEMP_REG0.b2, FAST_ONE_max_REG, 1
+        LSL     TEMP_REG0.b2, FAST_ONE_MAX_REG, 1
         ;clear max & min threshold hit
         OR      TEMP_REG0.b2, TEMP_REG0.b2, 0x41
         ;fast detect is enabled at a later stage
         OR      TEMP_REG0.b2, TEMP_REG0.b2, 0x80
-        .endif
+        
 
 SDFM_SKIP0_CH2:
 
@@ -828,7 +827,9 @@ config_osr_loop_end:
 ;
 ;
 config_sd_ch:
-         LDI    TEMP_REG0, 0
+        ;load fast detect enable bit
+        LBCO   &TEMP_REG3, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_SD_EN_FD_OFFSET, 1
+        LDI    TEMP_REG0, 0
         ; Load TR1.w0 <- SDFM_CFG_SD_CH_ID ;LDI      TEMP_REG1.w0, 0x210 =001100010000
 
         LBCO    &TEMP_REG1.w0, CT_PRU_ICSSG_LOC_DMEM,  SDFM_CFG_SD_CH_ID_OFFSET,  SDFM_CFG_SD_CH_ID_SZ
@@ -854,15 +855,15 @@ config_sd_ch:
         AND     TEMP_REG0.b2, TEMP_REG0.b2, PRUn_SD_ACC_SELi_MASK<<PRUn_SD_ACC_SELi_SHIFT
         OR      TEMP_REG0.b0, TEMP_REG0.b0, TEMP_REG0.b2
 
-        .if $isdefed("FD_CODE")
+        QBBC   SDFM_SKIP1_CH2, TEMP_REG3.b0, 0
         ; configure fast detect zero count
-        LBCO    &FAST_ZERO_min_REG, CT_PRU_ICSSG_LOC_DMEM,  SDFM_CFG_CH0_FD_ZERO_MIN_REG_OFFSET, 1
-        LBCO    &FAST_ZERO_max_REG, CT_PRU_ICSSG_LOC_DMEM,  SDFM_CFG_CH0_FD_ZERO_MAX_REG_OFFSET, 1
+        LBCO    &FAST_ZERO_MIN_REG, CT_PRU_ICSSG_LOC_DMEM,  SDFM_CFG_CH0_FD_ZERO_MIN_REG_OFFSET, 1
+        LBCO    &FAST_ZERO_MAX_REG, CT_PRU_ICSSG_LOC_DMEM,  SDFM_CFG_CH0_FD_ZERO_MAX_REG_OFFSET, 1
 
-        LSL     TEMP_REG0.b1, FAST_ZERO_min_REG, 3             ; r0.b1=120= 0111 1000
-        LSL     TEMP_REG0.b2, FAST_ZERO_max_REG, 1 ; r0.b2=30
+        LSL     TEMP_REG0.b1, FAST_ZERO_MIN_REG, 3             ; r0.b1=120= 0111 1000
+        LSL     TEMP_REG0.b2, FAST_ZERO_MAX_REG, 1 ; r0.b2=30
         OR      TEMP_REG0.b2, TEMP_REG0.b2, 0x41             ; clear hit flags; r0.b2 = 0101 1111 = 95
-        .endif
+        
 
         JMP    SDFM_SKIP1_CH2
 SDFM_SKIP1_CH0:
@@ -885,15 +886,15 @@ SDFM_SKIP1_CH0:
         AND     TEMP_REG0.b2, TEMP_REG0.b2, PRUn_SD_ACC_SELi_MASK<<PRUn_SD_ACC_SELi_SHIFT
         OR      TEMP_REG0.b0, TEMP_REG0.b0, TEMP_REG0.b2
 
-        .if $isdefed("FD_CODE")
+         QBBC   SDFM_SKIP1_CH2, TEMP_REG3.b0, 1
         ; configure fast detect zero count
-        LBCO    &FAST_ZERO_min_REG, CT_PRU_ICSSG_LOC_DMEM,  SDFM_CFG_CH1_FD_ZERO_MIN_REG_OFFSET, 1
-        LBCO    &FAST_ZERO_max_REG, CT_PRU_ICSSG_LOC_DMEM,  SDFM_CFG_CH1_FD_ZERO_MAX_REG_OFFSET, 1
+        LBCO    &FAST_ZERO_MIN_REG, CT_PRU_ICSSG_LOC_DMEM,  SDFM_CFG_CH1_FD_ZERO_MIN_REG_OFFSET, 1
+        LBCO    &FAST_ZERO_MAX_REG, CT_PRU_ICSSG_LOC_DMEM,  SDFM_CFG_CH1_FD_ZERO_MAX_REG_OFFSET, 1
 
-        LSL     TEMP_REG0.b1, FAST_ZERO_min_REG, 3             ; r0.b1=120= 0111 1000
-        LSL     TEMP_REG0.b2, FAST_ZERO_max_REG, 1 ; r0.b2=30
+        LSL     TEMP_REG0.b1, FAST_ZERO_MIN_REG, 3             ; r0.b1=120= 0111 1000
+        LSL     TEMP_REG0.b2, FAST_ZERO_MAX_REG, 1 ; r0.b2=30
         OR      TEMP_REG0.b2, TEMP_REG0.b2, 0x41             ; clear hit flags; r0.b2 = 0101 1111 = 95
-        .endif
+      
 
         JMP    SDFM_SKIP1_CH2
 SDFM_SKIP1_CH1:
@@ -916,15 +917,15 @@ SDFM_SKIP1_CH1:
         AND     TEMP_REG0.b2, TEMP_REG0.b2, PRUn_SD_ACC_SELi_MASK<<PRUn_SD_ACC_SELi_SHIFT
         OR      TEMP_REG0.b0, TEMP_REG0.b0, TEMP_REG0.b2
 
-        .if $isdefed("FD_CODE")
+        QBBC   SDFM_SKIP1_CH2, TEMP_REG3.b0, 2
         ; configure fast detect zero count
-        LBCO    &FAST_ZERO_min_REG, CT_PRU_ICSSG_LOC_DMEM,  SDFM_CFG_CH2_FD_ZERO_MIN_REG_OFFSET, 1
-        LBCO    &FAST_ZERO_max_REG, CT_PRU_ICSSG_LOC_DMEM,  SDFM_CFG_CH2_FD_ZERO_MAX_REG_OFFSET, 1
+        LBCO    &FAST_ZERO_MIN_REG, CT_PRU_ICSSG_LOC_DMEM,  SDFM_CFG_CH2_FD_ZERO_MIN_REG_OFFSET, 1
+        LBCO    &FAST_ZERO_MAX_REG, CT_PRU_ICSSG_LOC_DMEM,  SDFM_CFG_CH2_FD_ZERO_MAX_REG_OFFSET, 1
 
-        LSL     TEMP_REG0.b1, FAST_ZERO_min_REG, 3             ; r0.b1=120= 0111 1000
-        LSL     TEMP_REG0.b2, FAST_ZERO_max_REG, 1 ; r0.b2=30
+        LSL     TEMP_REG0.b1, FAST_ZERO_MIN_REG, 3             ; r0.b1=120= 0111 1000
+        LSL     TEMP_REG0.b2, FAST_ZERO_MAX_REG, 1 ; r0.b2=30
         OR      TEMP_REG0.b2, TEMP_REG0.b2, 0x41             ; clear hit flags; r0.b2 = 0101 1111 = 95
-        .endif
+      
 
 SDFM_SKIP1_CH2:
        ;configure source clock, clock inversion & ACC source for all connected channels
@@ -965,18 +966,27 @@ reset_sd_ch_hw_loop_end:
         JMP     RET_ADDR_REG
 
 
-      .if $isdefed("FD_CODE")
+    
 ;
-;EPWM trip generation configuration
+;PWM trip zone block configuration
 config_pwm_trip:
-       ;set trip mask
-       LDI    TEMP_REG1, 0x134
+       ;set trip mask       
+       ;PWM0 register offset 
+       LDI    TEMP_REG1, ICSSG_CFG_PWM0
        LBCO   &TEMP_REG0, CT_PRU_ICSSG_CFG, TEMP_REG1, 4
-       LDI  TEMP_REG0.b1, 0x02; trip mask
+       QBNE            SDFM_MASK_SKIP1_CH0,   SD_CH0_ID, 0
+       OR TEMP_REG0.b1, TEMP_REG0.b1, 1
+SDFM_MASK_SKIP1_CH0
+       QBNE            SDFM_MASK_SKIP1_CH1,   SD_CH1_ID, 1
+       OR TEMP_REG0.b1, TEMP_REG0.b1, 2
+SDFM_MASK_SKIP1_CH1       
+        QBNE            SDFM_MASK_SKIP1_CH2, SD_CH2_ID,	2
+        OR TEMP_REG0.b1, TEMP_REG0.b1, 4
+SDFM_MASK_SKIP1_CH2:           
        SBCO   &TEMP_REG0, CT_PRU_ICSSG_CFG, TEMP_REG1, 4
 
        JMP     RET_ADDR_REG
-      .endif
+      
 ;
 ; Initialize SD (eCAP PWM) clock
 ;
diff --git a/source/current_sense/sdfm/firmware/sdfm.h b/source/current_sense/sdfm/firmware/sdfm.h
index 4fc892b..0fbd909 100644
--- a/source/current_sense/sdfm/firmware/sdfm.h
+++ b/source/current_sense/sdfm/firmware/sdfm.h
@@ -100,11 +100,11 @@ __sdfm_h    .set    1
 ;Fast detect registers(using only in SDFM init)
 
         .asg R19.b0,  FAST_TZ_OUT_REG
-        .asg R19.b1,  FAST_window_REG
-        .asg R19.b2,  FAST_ONE_max_REG
-        .asg R19.b3,  FAST_ONE_min_REG
-        .asg R27.b0,  FAST_ZERO_max_REG
-        .asg R27.b1,  FAST_ZERO_min_REG
+        .asg R19.b1,  FAST_WINDOW_REG
+        .asg R19.b2,  FAST_ONE_MAX_REG
+        .asg R19.b3,  FAST_ONE_MIN_REG
+        .asg R27.b0,  FAST_ZERO_MAX_REG
+        .asg R27.b1,  FAST_ZERO_MIN_REG
 
 
 ;
@@ -151,7 +151,7 @@ ICSSG_CFG_GPCFG1                .set 0x000C ;  GP IO Configuration Register 1
 ICSSG_CFG_SPPC                  .set 0x0034 ;  Scratch PAD priority and config
 ICSSG_CFG_PRU0_SD0_CLK          .set 0x48
 ICSSG_CFG_PRU1_SD0_CLK          .set 0x94
-ICSSG_CFG_PWM1                   .set 0x134 ; PWM1 trip generation configuration
+ICSSG_CFG_PWM0                   .set 0x130 ; PWM0 configuration register offset 
 
 ;
 ; ICSSG_GPCFGn_REG:PR1_PRUn_GP_MUX_SEL, Controls the icss_wrap mux sel
diff --git a/source/current_sense/sdfm/firmware/sdfm_bin.h b/source/current_sense/sdfm/firmware/sdfm_bin.h
index 9f84296..9c4685d 100644
--- a/source/current_sense/sdfm/firmware/sdfm_bin.h
+++ b/source/current_sense/sdfm/firmware/sdfm_bin.h
@@ -21,9 +21,9 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x91340401,
 0x1f01e1e1,
 0x81340401,
-0x23010399,
+0x23010499,
 0x32800000,
-0x23010a99,
+0x23010b99,
 0x240c00c2,
 0x24000082,
 0x91021801,
@@ -47,12 +47,13 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x0b04e1e1,
 0x110fe1e2,
 0x10020256,
-0x23012499,
-0x23017499,
-0x23012899,
-0x23013999,
-0x23016b99,
+0x23012599,
+0x2301b199,
+0x23012999,
+0x23015999,
+0x23019e99,
 0x1f19fefe,
+0x2301a799,
 0x240fffd5,
 0x24ffff95,
 0x240000d4,
@@ -65,7 +66,7 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x81001a01,
 0x9114189a,
 0xd1009a02,
-0x21004200,
+0x21004300,
 0xc9019a26,
 0x10161602,
 0x09020202,
@@ -260,7 +261,7 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x10000000,
 0x24000b01,
 0x81000a01,
-0x2400b681,
+0x2400b781,
 0x810c0a81,
 0x24140081,
 0x81380a81,
@@ -295,28 +296,60 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x2effa381,
 0x2f052381,
 0x20990000,
+0x91181804,
 0x240000e1,
 0x91103882,
-0x3102000e,
+0x3102002c,
 0x110f0203,
-0x68160303,
+0x6816030d,
 0x911e1801,
-0x21013400,
-0x68360303,
+0xc9000424,
+0x912c1833,
+0x91301873,
+0x912f1853,
+0x10333321,
+0x09037341,
+0x12214121,
+0x09015341,
+0x13414141,
+0x13804141,
+0x21015400,
+0x6836030d,
 0x91621801,
-0x21013400,
-0x68560302,
+0xc9010417,
+0x91701833,
+0x91741873,
+0x91731853,
+0x10333321,
+0x09037341,
+0x12214121,
+0x09015341,
+0x13414141,
+0x13804141,
+0x21015400,
+0x6856030c,
 0x91a61801,
+0xc902040a,
+0x91b41833,
+0x91b81873,
+0x91b71853,
+0x10333321,
+0x09037341,
+0x12214121,
+0x09015341,
+0x13414141,
+0x13804141,
 0x0903e3e3,
 0x0104e3e3,
 0xe0e33801,
 0x0b04e2e2,
 0x20990000,
+0x91181804,
 0x240000e1,
 0x91103882,
-0x3102002f,
+0x31020041,
 0x110f0203,
-0x6816030e,
+0x68160314,
 0x24000081,
 0x91381841,
 0x09024141,
@@ -329,8 +362,14 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x09044141,
 0x11304141,
 0x12410101,
-0x21016600,
-0x6836030e,
+0xc900042e,
+0x912e183b,
+0x912d181b,
+0x09033b21,
+0x09011b41,
+0x13414141,
+0x21019900,
+0x68360314,
 0x24000081,
 0x917c1841,
 0x09024141,
@@ -343,8 +382,14 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x09044141,
 0x11304141,
 0x12410101,
-0x21016600,
-0x6856030d,
+0xc901041a,
+0x9172183b,
+0x9171181b,
+0x09033b21,
+0x09011b41,
+0x13414141,
+0x21019900,
+0x68560313,
 0x24000081,
 0x91c01841,
 0x09024141,
@@ -357,6 +402,12 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x09044141,
 0x11304141,
 0x12410101,
+0xc9020406,
+0x91b6183b,
+0x91b5181b,
+0x09033b21,
+0x09011b41,
+0x13414141,
 0x0903e3e3,
 0x0100e3e3,
 0xe0e33801,
@@ -371,6 +422,16 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x0b04e1e1,
 0x1f17ffff,
 0x20990000,
+0x240130e2,
+0x90e22481,
+0x69001602,
+0x13012121,
+0x69013602,
+0x13022121,
+0x69025602,
+0x13042121,
+0x80e22481,
+0x20990000,
 0x240280c1,
 0x24000081,
 0x81282381,
diff --git a/source/current_sense/sdfm/include/sdfm_api.h b/source/current_sense/sdfm/include/sdfm_api.h
index 5b11098..37790e5 100644
--- a/source/current_sense/sdfm/include/sdfm_api.h
+++ b/source/current_sense/sdfm/include/sdfm_api.h
@@ -296,6 +296,38 @@ void SDFM_setFilterOverSamplingRatio(sdfm_handle h_sdfm, uint16_t nc_osr);
  *
  */
 uint64_t SDFM_getFirmwareVersion(sdfm_handle h_sdfm);
+ /* 
+ *  \brief  This API Configure Fast detect block fields.
+ *
+ *  \param[in]  h_sdfm          SDFM handle
+ *  \param[in]  ch           current ch number
+ *  \param[in]  fdParms   array of fast detect fields. {window size, zero max count, zero min count, one max count, one min count}
+ *
+ *
+ *
+ */
+void SDFM_configFastDetect(sdfm_handle h_sdfm, uint8_t ch, uint8_t *fdParms);
+/* 
+ *  \brief This API returns the Trip status for the PWM trip zone block specified by pwmIns variable.
+ *
+ *  \param[in]  h_sdfm       SDFM handle
+ *  \param[in]  pwm           current PWM instance
+ *
+ *  \retval     Status of PWM Trip status bit 
+ *
+ */
+uint32_t SDFM_getPwmTripStatus(sdfm_handle h_sdfm, uint8_t pwmIns); 
+/* 
+ *  \brief  Clear PWM trip status for the PWM trip zone block specified by pwmIns variable.
+ *
+ *  \param[in]  h_sdfm       SDFM handle
+ *  \param[in]  pwm           current PWM instance
+ *
+ *
+ */
+void SDFM_clearPwmTripStatus(sdfm_handle h_sdfm, uint8_t pwmIns); 
+
+
 /** @} */
 
 #ifdef __cplusplus
diff --git a/source/current_sense/sdfm/include/sdfm_drv.h b/source/current_sense/sdfm/include/sdfm_drv.h
index c9c2d9a..067f3bc 100644
--- a/source/current_sense/sdfm/include/sdfm_drv.h
+++ b/source/current_sense/sdfm/include/sdfm_drv.h
@@ -39,6 +39,7 @@ extern "C" {
 #endif
 
 #include <drivers/soc.h>
+#include <drivers/pruicss.h>
 
 
 
@@ -201,8 +202,10 @@ typedef struct SDFM_ChCtrl_s
     volatile uint16_t    enable_comparator;
     /**< bit-field to set the output data format for individual SDFM channels, BitN:ChN */
     volatile uint16_t    output_data_format;
-    /**< reserved */
-    volatile uint16_t    reserved1;
+    /**< bit-field to enable fast detect  for individual SDFM channels, BitN:ChN, non-zero to enable */
+    volatile uint8_t    enFastDetect;
+     /**< reserved */
+     volatile uint8_t   reserved1;
     /**< reserved */
     volatile uint16_t    reserved2;
 
@@ -254,10 +257,16 @@ typedef struct SDFM_Cfg_s
     volatile uint8_t    osr;
     /**< sdfm threshold parms*/
     SDFM_ThresholdParms  sdfm_threshold_parms;
-    /**< Reserved*/
-    volatile uint32_t    reserved1;
-    /**< reserved */
-    volatile uint8_t    reserved2;
+    /**< Fast detect window size*/
+    volatile uint8_t   fd_window;
+    /**< Fast detect max count of zero*/
+    volatile uint8_t   fd_zero_max;
+    /**< Fast detect min count of zero*/
+    volatile uint8_t   fd_zero_min;
+    /**< Fast detect max count of one*/
+    volatile uint8_t   fd_one_max;
+    /**< Fast detect min count of one*/
+    volatile uint8_t   fd_one_min;
     /**< sdfm ch clock parms*/
     SDFM_ClkSourceParms  sdfm_clk_parms;
     /**< array to store the params for gpio toggle for different channels*/
@@ -318,6 +327,7 @@ typedef struct SDFM_s {
     uint8_t  iep_inc;
     SDFM_Interface * p_sdfm_interface;
     SDFM_SampleOutInterface *sampleOutputInterface;
+    void *pruss_cfg;
 } SDFM;