am64x/am243x: hdsl: Add retry for Udma_ringDequeueRaw if it fails
- Switch to polling mode for UDMA completion - In release mode, Udma_ringDequeueRaw() returns timeout - Update App_udmaTrpdInit() to do fixed configuration only once. This reduces the copy time. Fixes: PINDSW-6659 Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
This commit is contained in:
parent
db642b84db
commit
47060ba7b1
@ -161,8 +161,6 @@ HDSL_Interface gHdslInterfaceTrace[NUM_RESOURCES] __attribute__((aligned(128), s
|
|||||||
|
|
||||||
HwiP_Object gPRUHwiObject;
|
HwiP_Object gPRUHwiObject;
|
||||||
|
|
||||||
/* Semaphore to indicate transfer completion */
|
|
||||||
static SemaphoreP_Object gUdmaTestDoneSem;
|
|
||||||
/* UDMA TRPD Memory */
|
/* UDMA TRPD Memory */
|
||||||
uint8_t gUdmaTestTrpdMem[UDMA_TEST_TRPD_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
|
uint8_t gUdmaTestTrpdMem[UDMA_TEST_TRPD_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
|
||||||
#endif
|
#endif
|
||||||
@ -185,7 +183,10 @@ static void App_udmaTrpdInit(Udma_ChHandle chHandle,
|
|||||||
{
|
{
|
||||||
CSL_UdmapTR15 *pTr;
|
CSL_UdmapTR15 *pTr;
|
||||||
uint32_t cqRingNum = Udma_chGetCqRingNum(chHandle);
|
uint32_t cqRingNum = Udma_chGetCqRingNum(chHandle);
|
||||||
|
static uint32_t initDone = 0;
|
||||||
|
|
||||||
|
if(initDone == 0)
|
||||||
|
{
|
||||||
/* Make TRPD with TR15 TR type */
|
/* Make TRPD with TR15 TR type */
|
||||||
UdmaUtils_makeTrpdTr15(trpdMem, 1U, cqRingNum);
|
UdmaUtils_makeTrpdTr15(trpdMem, 1U, cqRingNum);
|
||||||
|
|
||||||
@ -220,10 +221,20 @@ static void App_udmaTrpdInit(Udma_ChHandle chHandle,
|
|||||||
pTr->ddim2 = (pTr->dicnt0 * pTr->dicnt1);
|
pTr->ddim2 = (pTr->dicnt0 * pTr->dicnt1);
|
||||||
pTr->ddim3 = (pTr->dicnt0 * pTr->dicnt1 * pTr->dicnt2);
|
pTr->ddim3 = (pTr->dicnt0 * pTr->dicnt1 * pTr->dicnt2);
|
||||||
pTr->daddr = (uint64_t) Udma_defaultVirtToPhyFxn(destBuf, 0U, NULL);
|
pTr->daddr = (uint64_t) Udma_defaultVirtToPhyFxn(destBuf, 0U, NULL);
|
||||||
|
|
||||||
/* Perform cache writeback */
|
/* Perform cache writeback */
|
||||||
CacheP_wb(trpdMem, UDMA_TEST_TRPD_SIZE, CacheP_TYPE_ALLD);
|
CacheP_wb(trpdMem, UDMA_TEST_TRPD_SIZE, CacheP_TYPE_ALLD);
|
||||||
|
|
||||||
|
initDone = 1;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
pTr = UdmaUtils_getTrpdTr15Pointer(trpdMem, 0U);
|
||||||
|
pTr->daddr = (uint64_t) Udma_defaultVirtToPhyFxn(destBuf, 0U, NULL);
|
||||||
|
/* Perform cache writeback */
|
||||||
|
CacheP_wb(trpdMem, UDMA_TEST_TRPD_SIZE, CacheP_TYPE_ALLD);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -243,30 +254,23 @@ void udma_copy(uint8_t *srcBuf, uint8_t *destBuf, uint32_t length)
|
|||||||
DebugP_assert(UDMA_SOK == retVal);
|
DebugP_assert(UDMA_SOK == retVal);
|
||||||
|
|
||||||
/* Wait for return descriptor in completion ring - this marks transfer completion */
|
/* Wait for return descriptor in completion ring - this marks transfer completion */
|
||||||
SemaphoreP_pend(&gUdmaTestDoneSem, SystemP_WAIT_FOREVER);
|
while(1)
|
||||||
|
{
|
||||||
retVal = Udma_ringDequeueRaw(Udma_chGetCqRingHandle(chHandle), &pDesc);
|
retVal = Udma_ringDequeueRaw(Udma_chGetCqRingHandle(chHandle), &pDesc);
|
||||||
DebugP_assert(UDMA_SOK == retVal);
|
if(UDMA_SOK == retVal)
|
||||||
|
{
|
||||||
/* Check TR response status */
|
/* Check TR response status */
|
||||||
CacheP_inv(trpdMem, UDMA_TEST_TRPD_SIZE, CacheP_TYPE_ALLD);
|
CacheP_inv(trpdMem, UDMA_TEST_TRPD_SIZE, CacheP_TYPE_ALLD);
|
||||||
|
|
||||||
trRespStatus = UdmaUtils_getTrpdTr15Response(trpdMem, 1U, 0U);
|
trRespStatus = UdmaUtils_getTrpdTr15Response(trpdMem, 1U, 0U);
|
||||||
//DebugP_log("\r\n.trRespStatus = %u ", trRespStatus);
|
|
||||||
DebugP_assert(CSL_UDMAP_TR_RESPONSE_STATUS_COMPLETE == trRespStatus);
|
DebugP_assert(CSL_UDMAP_TR_RESPONSE_STATUS_COMPLETE == trRespStatus);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
/* Validate data in destination memory */
|
/* Validate data in destination memory */
|
||||||
CacheP_inv(destBuf, length, CacheP_TYPE_ALLD);
|
CacheP_inv(destBuf, length, CacheP_TYPE_ALLD);
|
||||||
}
|
}
|
||||||
|
|
||||||
void App_udmaEventCb(Udma_EventHandle eventHandle, uint32_t eventType, void *appData)
|
|
||||||
{
|
|
||||||
if(UDMA_EVENT_TYPE_DMA_COMPLETION == eventType)
|
|
||||||
{
|
|
||||||
SemaphoreP_post(&gUdmaTestDoneSem);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static void HDSL_IsrFxn()
|
static void HDSL_IsrFxn()
|
||||||
{
|
{
|
||||||
static uint64_t h_frames_count = 0;
|
static uint64_t h_frames_count = 0;
|
||||||
@ -1245,7 +1249,7 @@ void hdsl_diagnostic_main(void *arg)
|
|||||||
uint8_t ureg;
|
uint8_t ureg;
|
||||||
|
|
||||||
#ifndef HDSL_MULTI_CHANNEL
|
#ifndef HDSL_MULTI_CHANNEL
|
||||||
int32_t retVal = UDMA_SOK, status;
|
int32_t retVal = UDMA_SOK;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Open drivers to open the UART driver for console */
|
/* Open drivers to open the UART driver for console */
|
||||||
@ -1255,8 +1259,6 @@ void hdsl_diagnostic_main(void *arg)
|
|||||||
#ifndef HDSL_MULTI_CHANNEL
|
#ifndef HDSL_MULTI_CHANNEL
|
||||||
/* UDMA initialization */
|
/* UDMA initialization */
|
||||||
chHandle = gConfigUdma0BlkCopyChHandle[0]; /* Has to be done after driver open */
|
chHandle = gConfigUdma0BlkCopyChHandle[0]; /* Has to be done after driver open */
|
||||||
status = SemaphoreP_constructBinary(&gUdmaTestDoneSem, 0);
|
|
||||||
DebugP_assert(SystemP_SUCCESS == status);
|
|
||||||
/* Channel enable */
|
/* Channel enable */
|
||||||
retVal = Udma_chEnable(chHandle);
|
retVal = Udma_chEnable(chHandle);
|
||||||
DebugP_assert(UDMA_SOK == retVal);
|
DebugP_assert(UDMA_SOK == retVal);
|
||||||
|
|||||||
@ -45,7 +45,6 @@ pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0";
|
|||||||
udma1.$name = "CONFIG_UDMA0";
|
udma1.$name = "CONFIG_UDMA0";
|
||||||
udma1.udmaBlkCopyChannel.create(1);
|
udma1.udmaBlkCopyChannel.create(1);
|
||||||
udma1.udmaBlkCopyChannel[0].$name = "CONFIG_UDMA_BLKCOPY_CH0";
|
udma1.udmaBlkCopyChannel[0].$name = "CONFIG_UDMA_BLKCOPY_CH0";
|
||||||
udma1.udmaBlkCopyChannel[0].intrEnable = true;
|
|
||||||
udma1.udmaBlkCopyChannel[0].transferCallbackFxn = "App_udmaEventCb";
|
udma1.udmaBlkCopyChannel[0].transferCallbackFxn = "App_udmaEventCb";
|
||||||
|
|
||||||
debug_log.enableUartLog = true;
|
debug_log.enableUartLog = true;
|
||||||
|
|||||||
@ -45,7 +45,6 @@ pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO1";
|
|||||||
udma1.$name = "CONFIG_UDMA0";
|
udma1.$name = "CONFIG_UDMA0";
|
||||||
udma1.udmaBlkCopyChannel.create(1);
|
udma1.udmaBlkCopyChannel.create(1);
|
||||||
udma1.udmaBlkCopyChannel[0].$name = "CONFIG_UDMA_BLKCOPY_CH0";
|
udma1.udmaBlkCopyChannel[0].$name = "CONFIG_UDMA_BLKCOPY_CH0";
|
||||||
udma1.udmaBlkCopyChannel[0].intrEnable = true;
|
|
||||||
udma1.udmaBlkCopyChannel[0].transferCallbackFxn = "App_udmaEventCb";
|
udma1.udmaBlkCopyChannel[0].transferCallbackFxn = "App_udmaEventCb";
|
||||||
|
|
||||||
debug_log.enableUartLog = true;
|
debug_log.enableUartLog = true;
|
||||||
|
|||||||
@ -45,7 +45,6 @@ pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0";
|
|||||||
udma1.$name = "CONFIG_UDMA0";
|
udma1.$name = "CONFIG_UDMA0";
|
||||||
udma1.udmaBlkCopyChannel.create(1);
|
udma1.udmaBlkCopyChannel.create(1);
|
||||||
udma1.udmaBlkCopyChannel[0].$name = "CONFIG_UDMA_BLKCOPY_CH0";
|
udma1.udmaBlkCopyChannel[0].$name = "CONFIG_UDMA_BLKCOPY_CH0";
|
||||||
udma1.udmaBlkCopyChannel[0].intrEnable = true;
|
|
||||||
udma1.udmaBlkCopyChannel[0].transferCallbackFxn = "App_udmaEventCb";
|
udma1.udmaBlkCopyChannel[0].transferCallbackFxn = "App_udmaEventCb";
|
||||||
|
|
||||||
debug_log.enableUartLog = true;
|
debug_log.enableUartLog = true;
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user