diff --git a/docs_src/docs/api_guide/device/am243x/release_notes_09_01_00.md b/docs_src/docs/api_guide/device/am243x/release_notes_09_01_00.md
index 4503b0c..d8b95f3 100644
--- a/docs_src/docs/api_guide/device/am243x/release_notes_09_01_00.md
+++ b/docs_src/docs/api_guide/device/am243x/release_notes_09_01_00.md
@@ -34,7 +34,7 @@ SYNC Mode support for 1 to 10 frames per cycle and 8 kHz to 50 kHz cycle frequen
 API support for Parameter Channel Long Message Read and Write                                   | Position Sense HDSL
 Add support for PIPE_D register for SensorHub Channel                                           | Position Sense HDSL
 Add support for PIPE_D register for SensorHub Channel                                           | Position Sense HDSL
-Long cable (upto 100 meters)                                                                    | Position Sense HDSL
+Long cable (upto 100 meters) with Free Run mode                                                  | Position Sense HDSL
 Two channel example with LP-AM243 + BP-AM2BLDCSERVO                                             | Position Sense HDSL
 Compare event based command trigger support                                                     | Position Sense Tamagawa
 Two channel example with LP-AM243 + BP-AM2BLDCSERVO                                             | Position Sense Tamagawa
@@ -104,8 +104,8 @@ Below features are not support on AM243X LAUNCHPAD due to SOC or board constrain
     <td> R5F
     <td> YES
     <td> FreeRTOS, NORTOS
-    <td> Single channel, Multi channel using three PRU cores (load share mode), Free Run mode, Sync mode, Short Message Read and Write, Long Message Read and Write, Pipeline Channel Data, Long cable (upto 100 meters), Boosterpack with AM243x-LP
-    <td> 225 MHz PRU-ICSSG Core Clock based firmware
+    <td> Single channel, Multi channel using three PRU cores (load share mode), Free Run mode, Sync mode, Short Message Read and Write, Long Message Read and Write, Pipeline Channel Data, Long cable (upto 100 meters) with single channel Free Run mode, Boosterpack with AM243x-LP
+    <td> 225 MHz PRU-ICSSG Core Clock based firmware, Multi-channel with long cables(100m length), Long cable (upto 100 meters) with sync mode
 </tr>
 <tr>
     <td> Tamagawa
@@ -212,6 +212,13 @@ Below features are not support on AM243X LAUNCHPAD due to SOC or board constrain
     <td> 9.0
     <td> -
 </tr>
+<tr>
+    <td> PINDSW-7473
+    <td> HDSL : 100 meter cable length does not work for Free Run mode in 300Mhz PRU clock
+    <td> Position Sense HDSL
+    <td> 9.0
+    <td> -
+</tr>
 </table>
 
 ## Known Issues
@@ -280,6 +287,13 @@ Below features are not support on AM243X LAUNCHPAD due to SOC or board constrain
     <td> 9.0 onwards
     <td> -
 </tr>
+<tr>
+    <td> PINDSW-7474
+    <td> HDSL : 100 meter cable length does not work for sync mode in 300Mhz PRU clock
+    <td> Position Sense HDSL
+    <td> 9.0
+    <td> -
+</tr>
 </table>
 
 <!-- ## Errata
diff --git a/source/position_sense/hdsl/firmware/datalink_init.asm b/source/position_sense/hdsl/firmware/datalink_init.asm
index 113115c..3485058 100644
--- a/source/position_sense/hdsl/firmware/datalink_init.asm
+++ b/source/position_sense/hdsl/firmware/datalink_init.asm
@@ -597,12 +597,9 @@ aaa1:
 	loop aaa2,4
 	CALL3 PUSH_FIFO_2B_8x
 aaa2:
-
-;	PUSH 8 bytes for 1 byte data (0xcb) in FIFO
-	ldi FIFO_L,0xcb
-	loop aaa3,4
-	CALL3 PUSH_FIFO_2B_8x
-aaa3:
+	CALL2 WAIT_TX_FIFO_FREE
+	PUSH_FIFO_CONST		0xff
+	PUSH_FIFO_CONST		0xff
 
     .else
 ;add stuffing to gain processing time
@@ -638,6 +635,13 @@ datalink_learn_delay:
 
 	CALL1		check_test_pattern
 	qbeq		datalink_abort2, LOOP_CNT.b3, 14
+	.if !$defined(EXT_SYNC_ENABLE)
+	;	PUSH 6 bit stuffing in FIFO
+	ldi FIFO_L,0x2c
+	loop aaa3,3
+	CALL3 PUSH_FIFO_2B_8x
+aaa3:
+	.endif
 	qbne		datalink_learn_delay, REG_FNC.b0, 1
 datalink_learn_end_test:
 ; SLAVE_DELAY has no switch bit
diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h
index 76e9e4b..16fb8b8 100644
--- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h
+++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h
@@ -425,7 +425,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
 0x230257dd,
 0x2400ff1e,
 0x2400ff1e,
-0x21059d00,
+0x2105a000,
 0x51000c1e,
 0x51015b04,
 0x100c0c02,
@@ -752,7 +752,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
 0x24003001,
 0xd1066b0e,
 0x2400010d,
-0x23058fd1,
+0x230592d1,
 0x68ab8d45,
 0x13803b3b,
 0x913d1880,
@@ -765,7 +765,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
 0x81531800,
 0x7900003b,
 0x2400020d,
-0x23058fd1,
+0x230592d1,
 0x688b8d38,
 0x8137184b,
 0x13803b3b,
@@ -808,7 +808,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
 0x1d09c4c4,
 0x2400040d,
 0x24003001,
-0x23058fd1,
+0x230592d1,
 0x15ff8d9c,
 0x69005c34,
 0x51009c33,
@@ -1117,7 +1117,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
 0x6905001e,
 0x24000100,
 0x81821800,
-0x23057b9d,
+0x23057e9d,
 0x240002c0,
 0x24580080,
 0xf1002081,
@@ -1205,7 +1205,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
 0x9101185b,
 0x51005b0e,
 0x7900000d,
-0x2306c4d1,
+0x2306c7d1,
 0x91dc388c,
 0x240000e2,
 0x91e21882,
@@ -1213,7 +1213,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
 0x100c0c2a,
 0x106c6c4a,
 0x102c2c6a,
-0x2306c4d1,
+0x2306c7d1,
 0x0b01e2e2,
 0x0501e2e2,
 0x4f00e2ff,
@@ -1289,7 +1289,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
 0x10000020,
 0x2d802101,
 0x910c3c82,
-0x58e3e230,
+0x58e3e233,
 0x04e2e3eb,
 0x100b0b02,
 0x0b01ebeb,
@@ -1317,9 +1317,9 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
 0x2400b279,
 0x31030002,
 0x23024a99,
-0x2400cb79,
-0x31030002,
-0x23024a99,
+0x230257dd,
+0x2400ff1e,
+0x2400ff1e,
 0x24000065,
 0x69012501,
 0x01016565,
@@ -1330,12 +1330,15 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
 0x0b077200,
 0x12001313,
 0x0901f2f2,
-0x2306b8d1,
-0x510e6506,
-0x6f010df6,
+0x2306bbd1,
+0x510e6509,
+0x24002c79,
+0x31020002,
+0x23024a99,
+0x6f010df3,
 0x10656546,
 0x05012525,
-0x4f00259e,
+0x4f00259b,
 0x79000011,
 0xd118fe02,
 0xd105ff00,
@@ -1352,12 +1355,12 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
 0xf1000100,
 0x1f070000,
 0xe1000100,
-0x7f000011,
+0x7f00000e,
 0x24000925,
 0x24001b8d,
 0x23014b9d,
 0x2300049d,
-0x2306b8d1,
+0x2306bbd1,
 0x6f010ded,
 0x05012525,
 0x4f0025fa,
@@ -1365,7 +1368,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
 0x24001c8d,
 0x23014b9d,
 0x2300049d,
-0x2306b8d1,
+0x2306bbd1,
 0x6f010de3,
 0x05012525,
 0x4f0025fa,
@@ -1418,7 +1421,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
 0x81723881,
 0x24000100,
 0x81821800,
-0x23057b9d,
+0x23057e9d,
 0x240002c0,
 0x24580080,
 0xf1002081,
@@ -1454,7 +1457,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
 0x1d007e7e,
 0x2301f6d1,
 0x2301e2d1,
-0x21065f00,
+0x21066200,
 0x91831821,
 0xc9002104,
 0x240000e0,
@@ -1608,7 +1611,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
 0x108787c7,
 0x04c98087,
 0x108080c9,
-0x23063ed1,
+0x230641d1,
 0x108b8b9d,
 0x91aa1800,
 0x1f018000,
@@ -1631,7 +1634,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
 0x108787c7,
 0x04c98087,
 0x108080c9,
-0x23063ed1,
+0x230641d1,
 0x91983880,
 0x10eeeee1,
 0x24000061,
@@ -1745,11 +1748,11 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
 0x23021dd1,
 0x1d03c4c4,
 0x2301e2d1,
-0x2305e69d,
+0x2305e99d,
 0x05014545,
 0x51074512,
 0x49004502,
-0x2106ac00,
+0x2106af00,
 0x230257dd,
 0x2400ff1e,
 0x2400001e,
diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h
index d6f2a5c..5549951 100644
--- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h
+++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h
@@ -425,7 +425,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
 0x230257dd,
 0x2400ff1e,
 0x2400ff1e,
-0x21057100,
+0x21057400,
 0x51000c1e,
 0x51015b04,
 0x100c0c02,
@@ -752,7 +752,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
 0x24003001,
 0xd1066b0e,
 0x2400010d,
-0x230563d1,
+0x230566d1,
 0x68ab8d45,
 0x13803b3b,
 0x913d1880,
@@ -765,7 +765,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
 0x81531800,
 0x7900003b,
 0x2400020d,
-0x230563d1,
+0x230566d1,
 0x688b8d38,
 0x8137184b,
 0x13803b3b,
@@ -808,7 +808,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
 0x1d09c4c4,
 0x2400040d,
 0x24003001,
-0x230563d1,
+0x230566d1,
 0x15ff8d9c,
 0x69005c34,
 0x51009c33,
@@ -1117,7 +1117,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
 0x69050009,
 0x24000100,
 0x81821800,
-0x23054f9d,
+0x2305529d,
 0x240000e0,
 0xf1820001,
 0x6f0001fe,
@@ -1185,7 +1185,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
 0x9101185b,
 0x51005b0e,
 0x7900000d,
-0x230698d1,
+0x23069bd1,
 0x91dc388c,
 0x240000e2,
 0x91e21882,
@@ -1193,7 +1193,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
 0x100c0c2a,
 0x106c6c4a,
 0x102c2c6a,
-0x230698d1,
+0x23069bd1,
 0x0b01e2e2,
 0x0501e2e2,
 0x4f00e2ff,
@@ -1269,7 +1269,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
 0x10000020,
 0x2d802101,
 0x910c3c82,
-0x58e3e230,
+0x58e3e233,
 0x04e2e3eb,
 0x100b0b02,
 0x0b01ebeb,
@@ -1297,9 +1297,9 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
 0x2400b279,
 0x31030002,
 0x23024a99,
-0x2400cb79,
-0x31030002,
-0x23024a99,
+0x230257dd,
+0x2400ff1e,
+0x2400ff1e,
 0x24000065,
 0x69012501,
 0x01016565,
@@ -1310,12 +1310,15 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
 0x0b077200,
 0x12001313,
 0x0901f2f2,
-0x23068cd1,
-0x510e6506,
-0x6f010df6,
+0x23068fd1,
+0x510e6509,
+0x24002c79,
+0x31020002,
+0x23024a99,
+0x6f010df3,
 0x10656546,
 0x05012525,
-0x4f00259e,
+0x4f00259b,
 0x79000011,
 0xd119fe02,
 0xd10dff00,
@@ -1332,12 +1335,12 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
 0xf1000100,
 0x1f070000,
 0xe1000100,
-0x7f000025,
+0x7f000022,
 0x24000925,
 0x24001b8d,
 0x23014b9d,
 0x2300049d,
-0x23068cd1,
+0x23068fd1,
 0x6f010ded,
 0x05012525,
 0x4f0025fa,
@@ -1345,7 +1348,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
 0x24001c8d,
 0x23014b9d,
 0x2300049d,
-0x23068cd1,
+0x23068fd1,
 0x6f010de3,
 0x05012525,
 0x4f0025fa,
@@ -1398,7 +1401,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
 0x81723881,
 0x24000100,
 0x81821800,
-0x23054f9d,
+0x2305529d,
 0x240000e0,
 0xf1820001,
 0x6f0001fe,
@@ -1410,7 +1413,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
 0x1d017e7e,
 0x2301f6d1,
 0x2301e2d1,
-0x21063300,
+0x21063600,
 0x91831821,
 0xc9002104,
 0x240000e0,
@@ -1564,7 +1567,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
 0x108787c7,
 0x04c98087,
 0x108080c9,
-0x230612d1,
+0x230615d1,
 0x108b8b9d,
 0x91aa1800,
 0x1f018000,
@@ -1587,7 +1590,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
 0x108787c7,
 0x04c98087,
 0x108080c9,
-0x230612d1,
+0x230615d1,
 0x91983880,
 0x10eeeee1,
 0x24000061,
@@ -1701,11 +1704,11 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
 0x23021dd1,
 0x1d03c4c4,
 0x2301e2d1,
-0x2305ba9d,
+0x2305bd9d,
 0x05014545,
 0x51074512,
 0x49004502,
-0x21068000,
+0x21068300,
 0x230257dd,
 0x2400ff1e,
 0x2400001e,
diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch2_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch2_bin.h
index 63e2aca..c062f65 100644
--- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch2_bin.h
+++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch2_bin.h
@@ -1821,7 +1821,7 @@ const uint8_t Hiperface_DSL2_0_TX_PRU_1[] = {
 0x3c,
 0x0c,
 0x91,
-0x30,
+0x33,
 0xe2,
 0xe3,
 0x58,
@@ -1933,18 +1933,18 @@ const uint8_t Hiperface_DSL2_0_TX_PRU_1[] = {
 0x4a,
 0x02,
 0x23,
-0x79,
-0xcb,
-0x00,
-0x24,
-0x02,
-0x00,
-0x03,
-0x31,
-0x99,
-0x4a,
+0xdd,
+0x57,
 0x02,
 0x23,
+0x1e,
+0xff,
+0x00,
+0x24,
+0x1e,
+0xff,
+0x00,
+0x24,
 0x65,
 0x00,
 0x00,
@@ -1989,11 +1989,23 @@ const uint8_t Hiperface_DSL2_0_TX_PRU_1[] = {
 0x5f,
 0x04,
 0x23,
-0x06,
+0x09,
 0x65,
 0x0e,
 0x51,
-0xf6,
+0x79,
+0x2c,
+0x00,
+0x24,
+0x02,
+0x00,
+0x02,
+0x31,
+0x99,
+0x4a,
+0x02,
+0x23,
+0xf3,
 0x0d,
 0x01,
 0x6f,
@@ -2005,7 +2017,7 @@ const uint8_t Hiperface_DSL2_0_TX_PRU_1[] = {
 0x25,
 0x01,
 0x05,
-0x9e,
+0x9b,
 0x25,
 0x00,
 0x4f,
@@ -2073,7 +2085,7 @@ const uint8_t Hiperface_DSL2_0_TX_PRU_1[] = {
 0x01,
 0x00,
 0xe1,
-0xe5,
+0xe2,
 0x00,
 0x00,
 0x7d,
@@ -3471,7 +3483,7 @@ const uint8_t Hiperface_DSL2_0_TX_PRU_2[] = {
 0x11,
 0x00,
 0x00,
-0x80,
+0x8c,
 0x04,
 0x00,
 0x00,
@@ -3479,7 +3491,7 @@ const uint8_t Hiperface_DSL2_0_TX_PRU_2[] = {
 0x00,
 0x01,
 0x00,
-0x80,
+0x8c,
 0x19,
 0x00,
 0x00,