diff --git a/source/position_sense/hdsl/firmware/defines.inc b/source/position_sense/hdsl/firmware/defines.inc
index 179f40a..b0be80d 100644
--- a/source/position_sense/hdsl/firmware/defines.inc
+++ b/source/position_sense/hdsl/firmware/defines.inc
@@ -35,7 +35,7 @@ FIRMWARE_VERSION_CODING .set            0x1
 ;  bit5..4		major number
 FIRMWARE_VERSION_MAJOR	.set			0x0
 ;  bit3..0		minor number
-FIRMWARE_VERSION_MINOR	.set			0x3
+FIRMWARE_VERSION_MINOR	.set			0x4
 
 ICSS_FIRMWARE_RELEASE	.set            ((FIRMWARE_VERSION_CODING << 6) | (FIRMWARE_VERSION_MAJOR << 4) | (FIRMWARE_VERSION_MINOR << 0))
 
diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h
index 9167ea6..7299a62 100644
--- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h
+++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h
@@ -704,16 +704,16 @@ const unsigned int Hiperface_DSL2_0[]= {
 0x10121221,
 0x81601881,
 0xd104c40e,
-0x91521801,
-0x11db0101,
+0x91521802,
+0x11db0202,
 0x5100980c,
 0x913d1880,
 0x1f050000,
 0x813d1800,
 0xc9052002,
 0x2400269f,
-0x1f050101,
-0x81521801,
+0x1f050202,
+0x81521802,
 0x2400060d,
 0x040d6666,
 0x230252d1,
@@ -727,10 +727,10 @@ const unsigned int Hiperface_DSL2_0[]= {
 0x813d1800,
 0xc9042002,
 0x2400269f,
-0x1f020101,
-0x81521801,
+0x1f020202,
+0x81521802,
 0x79000033,
-0x81521801,
+0x81521802,
 0x0908f3e2,
 0x10727202,
 0x91a45800,
diff --git a/source/position_sense/hdsl/firmware/transport.asm b/source/position_sense/hdsl/firmware/transport.asm
index d1d20e2..9471fc4 100644
--- a/source/position_sense/hdsl/firmware/transport.asm
+++ b/source/position_sense/hdsl/firmware/transport.asm
@@ -111,8 +111,8 @@ transport_on_v_frame:
 	sbco		&REG_TMP1, MASTER_REGS_CONST, VPOSCRC_TEMP, 2
 ;transmission error?
 	qbbs		transport_on_v_frame_dont_update_qm, H_FRAME.flags, FLAG_ERR_VERT
-    lbco		&REG_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
-    and         REG_TMP1.b0, REG_TMP1.b0, (~((1<<ONLINE_STATUS_1_SCE) | (1<<ONLINE_STATUS_1_VPOS)) & 0xFF)
+    lbco		&REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
+    and         REG_TMP2.b0, REG_TMP2.b0, (~((1<<ONLINE_STATUS_1_SCE) | (1<<ONLINE_STATUS_1_VPOS)) & 0xFF)
 ;checking for crc error
 	qbeq		check_for_slave_error_on_v_frame, CRC_VERT, 0
 ; Set EVENT_S_SCE in EVENT register
@@ -125,8 +125,8 @@ transport_on_v_frame:
 	ldi		r31.w0, PRU0_ARM_IRQ4
 update_events_no_int4:
 ; Set ONLINE_STATUS_1_SCE in ONLINE_STATUS_1 register
-    set         REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_1_SCE
-    sbco		&REG_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
+    set         REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_1_SCE
+    sbco		&REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
 	QM_SUB		6
 transport_on_v_frame_dont_update_qm:
 ;update CRC error count
@@ -138,6 +138,7 @@ transport_on_v_frame_dont_update_qm:
 	qba		transport_on_v_frame_exit
 check_for_slave_error_on_v_frame:
 ;CRC was correct -> add 1 to QM
+;Note: QM_ADD uses REG_TMP1
 	QM_ADD		1
 ;check for special character: K29.7 is sent in first byte of vertical channel if slave error occured
 	qbne		transport_on_v_frame_check_pos, VERT_H.b3, K29_7
@@ -151,11 +152,11 @@ check_for_slave_error_on_v_frame:
 	ldi		r31.w0, PRU0_ARM_IRQ4
 update_events_no_int5:
 ; Set ONLINE_STATUS_1_VPOS in ONLINE_STATUS_1 register
-    set         REG_TMP1.b0, REG_TMP1.b0, ONLINE_STATUS_1_VPOS
-    sbco		&REG_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
+    set         REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_1_VPOS
+    sbco		&REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
 	qba		transport_on_v_frame_exit
 transport_on_v_frame_check_pos:
-	sbco		&REG_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
+	sbco		&REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
 	lsl		REG_TMP2, CHANNEL.ch_verth, 8
 	mov		REG_TMP2.b0, VERT_L.b3
 ;first V-Frame? -> update FAST POS with SAFE POS