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am243x/am64x: hdsl: Fix reset issue with certain encoders

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- Revert commit af129481c2 for free run mode
- Add a separate build macro for SYNC mode

Fixes: PINDSW-7126

Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
This commit is contained in:
Dhaval Khandla 2023-12-18 17:10:16 +05:30
parent 047c1db56a
commit 0324024e00
19 changed files with 90 additions and 82 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
source/position_sense/hdsl/firmware/datalink.asm
View File

@ -453,7 +453,7 @@ push_2B_0:
.else
PUSH_FIFO_CONST 0x03
.endif
.if $defined("FREERUN_300_MHZ")
.if $defined("FREERUN_300_MHZ") | $defined("SYNC_300_MHZ")
ldi REG_TMP0, (6*(CLKDIV_FAST+1)-8+2)
.else
ldi REG_TMP0, (6*(CLKDIV_FAST+1)-8)
@ -1839,7 +1839,7 @@ send_trailer:
NOP_2
NOP_2
NOP_2
.if $defined("FREERUN_300_MHZ")
.if $defined("FREERUN_300_MHZ") | $defined("SYNC_300_MHZ")
NOP_2
NOP_2
NOP_2
@ -1946,7 +1946,7 @@ qm_add_end:
;--------------------------------------------------------------------------------------------------
wait_delay:
WAIT_TX_DONE
.if $defined("FREERUN_300_MHZ")
.if $defined("FREERUN_300_MHZ") | $defined("SYNC_300_MHZ")
NOP_2
NOP_2
NOP_2
@ -1957,6 +1957,10 @@ wait_delay:
NOP_2
NOP_2
.endif
.if $defined("FREERUN_300_MHZ")
NOP_2
NOP_2
.endif
.if $defined("HDSL_MULTICHANNEL")
NOP_2
NOP_2

8
source/position_sense/hdsl/firmware/datalink_init.asm
View File

@ -275,7 +275,7 @@ datalink_learn:
.endif
; indication of TX_DONE comes about 53ns after wire timing
WAIT_TX_DONE
.if $defined("FREERUN_300_MHZ")
.if $defined("FREERUN_300_MHZ") | $defined("SYNC_300_MHZ")
NOP_2
NOP_2
NOP_2
@ -377,7 +377,7 @@ datalink_learn_skip_one_bit_1:
; pre-load register to save time on last bit
; ldi REG_TMP2, (74*CYCLES_BIT-9) ; 100 m
.if $defined("FREERUN_300_MHZ")
.if $defined("FREERUN_300_MHZ") | $defined("SYNC_300_MHZ")
ldi r3, (74*CYCLES_BIT+9)
.else
ldi r3, (74*CYCLES_BIT+9)
@ -451,7 +451,7 @@ push_3b_0:
NOP_2
NOP_2
NOP_2
.if $defined("FREERUN_300_MHZ")
.if $defined("FREERUN_300_MHZ") | $defined("SYNC_300_MHZ")
NOP_2
NOP_2
NOP_2
@ -568,7 +568,7 @@ datalink_learn_end:
datalink_abort2:
qbbs datalink_abort2_no_wait, r30, RX_ENABLE ;changed here from 24 to 26
WAIT_TX_DONE
.if $defined("FREERUN_300_MHZ")
.if $defined("FREERUN_300_MHZ") | $defined("SYNC_300_MHZ")
LOOP no_operation_2cycle,9
NOP_2
no_operation_2cycle:

2
source/position_sense/hdsl/firmware/defines.inc
View File

@ -39,7 +39,7 @@ FIRMWARE_VERSION_MINOR .set 0xB
ICSS_FIRMWARE_RELEASE .set ((FIRMWARE_VERSION_MAJOR << 4) | (FIRMWARE_VERSION_MINOR << 0))
;number of cycles for 1 bit
.if $defined("FREERUN_300_MHZ")
.if $isdefed("FREERUN_300_MHZ") | $isdefed("SYNC_300_MHZ")
;number of cycles for 1 bit
CYCLES_BIT .set 32
;clock divider

58
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h
View File

@ -56,7 +56,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x91003c82,
0x1308e2e2,
0x81003c82,
0x21063400,
0x21063600,
0x21000000,
0x2eff8f8e,
0x24000725,
@ -120,7 +120,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x230330d1,
0x1d03c4c4,
0x2302cfd1,
0x2305a19d,
0x2305a39d,
0x05014545,
0x51074514,
0x49004502,
@ -162,7 +162,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x10000020,
0x0b018001,
0x14000130,
0x230356d1,
0x230358d1,
0x6f0005f6,
0x24001d05,
0xc918ff00,
@ -174,7 +174,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x10000020,
0x0b018001,
0x14000130,
0x230356d1,
0x230358d1,
0x6f0105f6,
0xc918ff00,
0x101f1f00,
@ -275,7 +275,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230356d1,
0x230358d1,
0x6f0005f7,
0x240120eb,
0xf0cd0b0d,
@ -294,7 +294,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230356d1,
0x230358d1,
0x6f0005f7,
0x24000001,
0x1c2d5050,
@ -317,7 +317,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1f00cdcd,
0x0b018021,
0x14002130,
0x230356d1,
0x230358d1,
0x110fcdc0,
0x240168eb,
0xf0c00b00,
@ -342,7 +342,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230356d1,
0x230358d1,
0x6f0005f7,
0x240120eb,
0xf0cd0b0d,
@ -361,7 +361,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230356d1,
0x230358d1,
0x6f0005f7,
0x24000001,
0x1c2d5050,
@ -384,7 +384,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1f00cdcd,
0x0b018021,
0x14002130,
0x230356d1,
0x230358d1,
0x110fcdc0,
0x240168eb,
0xf0c00b00,
@ -578,14 +578,14 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xd703ffff,
0x2400001e,
0x2400ff1e,
0x2103a100,
0x2103a300,
0x69074507,
0xc901c405,
0xd104ff00,
0xd703ffff,
0x2400ff1e,
0x2400ff1e,
0x2103f500,
0x2103f700,
0x51000c2d,
0x51015b04,
0x100c0c02,
@ -694,7 +694,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x79000002,
0x2400ff1e,
0x09017979,
0x21051400,
0x21051600,
0xd1077905,
0xd104ff00,
0xd703ffff,
@ -746,12 +746,12 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xd1047905,
0x106d6d79,
0x2400037b,
0x21035b00,
0x21035d00,
0x2102ba00,
0x106d6d79,
0x2400027b,
0x21035b00,
0x21043f00,
0x21035d00,
0x21044100,
0xd104ff00,
0xd703ffff,
0xd1074d03,
@ -867,7 +867,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x91a91800,
0x01010000,
0x81a91800,
0x21063400,
0x21063600,
0x20d10000,
0x117f6666,
0xc9066604,
@ -896,6 +896,8 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x31010001,
0x31010001,
0x31010001,
0x31010001,
0x31010001,
0x1f007e7e,
0x810c3c80,
0x24000c10,
@ -945,7 +947,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x2400017b,
0x2102bb00,
0x2400017b,
0x21043f00,
0x21044100,
0xd104ff00,
0xd703ffff,
0xd1077903,
@ -973,7 +975,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x2400ff1e,
0x09017979,
0x2400017b,
0x21043f00,
0x21044100,
0x2eff838e,
0x24003f00,
0x81401800,
@ -1035,7 +1037,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x686e5303,
0x24000019,
0x79000002,
0x230614d1,
0x230616d1,
0x10535300,
0x10333320,
0x10131340,
@ -1047,7 +1049,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x815618c4,
0x815818d8,
0x81637894,
0x2103e800,
0x2103ea00,
0x31010004,
0xd104ff00,
0xd703ffff,
@ -1242,7 +1244,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x24003001,
0xd1066b0e,
0x2400010d,
0x230776d1,
0x230778d1,
0x68ab8d45,
0x13803b3b,
0x913d1880,
@ -1255,7 +1257,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x81531800,
0x7900003b,
0x2400020d,
0x230776d1,
0x230778d1,
0x688b8d38,
0x8137184b,
0x13803b3b,
@ -1298,7 +1300,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x1d09c4c4,
0x2400040d,
0x24003001,
0x230776d1,
0x230778d1,
0x15ff8d9c,
0x69005c34,
0x51009c33,
@ -1541,7 +1543,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xd703ffff,
0x2400001e,
0x2400001e,
0x2305fbd1,
0x2305fdd1,
0x108b8b9d,
0x91aa1800,
0x1f018000,
@ -1565,7 +1567,7 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0xd703ffff,
0x2400001e,
0x2400001e,
0x2305fbd1,
0x2305fdd1,
0x91983880,
0x10eeeee1,
0x24000061,
@ -1655,11 +1657,11 @@ const uint32_t Hiperface_DSL2_0_RTU_0[] = {
0x81080580,
0x240003c0,
0x810605c0,
0x24000a00,
0x24000b00,
0x810b1800,
0x81441800,
0x2eff8383,
0x2303999d,
0x23039b9d,
0x24000866,
0x2400000c,
0x2400002c,

2
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h
View File

@ -1787,7 +1787,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_RTU_0[] = {
0x81080580,
0x240003c0,
0x810605c0,
0x24000a00,
0x24000b00,
0x810b1800,
0x81441800,
0x2eff8383,

58
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h
View File

@ -56,7 +56,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x91003c82,
0x1308e2e2,
0x81003c82,
0x21063400,
0x21063600,
0x21000000,
0x2eff8f8e,
0x24000725,
@ -120,7 +120,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x230330d1,
0x1d03c4c4,
0x2302cfd1,
0x2305a19d,
0x2305a39d,
0x05014545,
0x51074514,
0x49004502,
@ -162,7 +162,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x10000020,
0x0b018001,
0x14000130,
0x230356d1,
0x230358d1,
0x6f0005f6,
0x24001d05,
0xc919ff00,
@ -174,7 +174,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x10000020,
0x0b018001,
0x14000130,
0x230356d1,
0x230358d1,
0x6f0105f6,
0xc919ff00,
0x103f3f00,
@ -275,7 +275,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230356d1,
0x230358d1,
0x6f0005f7,
0x240820eb,
0xf0cd0b0d,
@ -294,7 +294,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230356d1,
0x230358d1,
0x6f0005f7,
0x24000001,
0x1c2d5050,
@ -317,7 +317,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1f00cdcd,
0x0b018021,
0x14002130,
0x230356d1,
0x230358d1,
0x110fcdc0,
0x240868eb,
0xf0c00b00,
@ -342,7 +342,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230356d1,
0x230358d1,
0x6f0005f7,
0x240820eb,
0xf0cd0b0d,
@ -361,7 +361,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1e05cdcd,
0x0b018001,
0x14000130,
0x230356d1,
0x230358d1,
0x6f0005f7,
0x24000001,
0x1c2d5050,
@ -384,7 +384,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1f00cdcd,
0x0b018021,
0x14002130,
0x230356d1,
0x230358d1,
0x110fcdc0,
0x240868eb,
0xf0c00b00,
@ -578,14 +578,14 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0xd70bffff,
0x2400001e,
0x2400ff1e,
0x2103a100,
0x2103a300,
0x69074507,
0xc901c405,
0xd10cff00,
0xd70bffff,
0x2400ff1e,
0x2400ff1e,
0x2103f500,
0x2103f700,
0x51000c2d,
0x51015b04,
0x100c0c02,
@ -694,7 +694,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x79000002,
0x2400ff1e,
0x09017979,
0x21051400,
0x21051600,
0xd1077905,
0xd10cff00,
0xd70bffff,
@ -746,12 +746,12 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0xd1047905,
0x106d6d79,
0x2400037b,
0x21035b00,
0x21035d00,
0x2102ba00,
0x106d6d79,
0x2400027b,
0x21035b00,
0x21043f00,
0x21035d00,
0x21044100,
0xd10cff00,
0xd70bffff,
0xd1074d03,
@ -867,7 +867,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x91a91800,
0x01010000,
0x81a91800,
0x21063400,
0x21063600,
0x20d10000,
0x117f6666,
0xc9066604,
@ -896,6 +896,8 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x31010001,
0x31010001,
0x31010001,
0x31010001,
0x31010001,
0x1f017e7e,
0x810c3c80,
0x24000c10,
@ -945,7 +947,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x2400017b,
0x2102bb00,
0x2400017b,
0x21043f00,
0x21044100,
0xd10cff00,
0xd70bffff,
0xd1077903,
@ -973,7 +975,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x2400ff1e,
0x09017979,
0x2400017b,
0x21043f00,
0x21044100,
0x2eff838e,
0x24003f00,
0x81401800,
@ -1035,7 +1037,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x686e5303,
0x24000019,
0x79000002,
0x230614d1,
0x230616d1,
0x10535300,
0x10333320,
0x10131340,
@ -1047,7 +1049,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x815618c4,
0x815818d8,
0x81637894,
0x2103e800,
0x2103ea00,
0x31010004,
0xd10cff00,
0xd70bffff,
@ -1242,7 +1244,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x24003001,
0xd1066b0e,
0x2400010d,
0x230777d1,
0x230779d1,
0x68ab8d45,
0x13803b3b,
0x913d1880,
@ -1255,7 +1257,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x81531800,
0x7900003b,
0x2400020d,
0x230777d1,
0x230779d1,
0x688b8d38,
0x8137184b,
0x13803b3b,
@ -1298,7 +1300,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x1d09c4c4,
0x2400040d,
0x24003001,
0x230777d1,
0x230779d1,
0x15ff8d9c,
0x69005c34,
0x51009c33,
@ -1541,7 +1543,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0xd70bffff,
0x2400001e,
0x2400001e,
0x2305fbd1,
0x2305fdd1,
0x108b8b9d,
0x91aa1800,
0x1f018000,
@ -1565,7 +1567,7 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0xd70bffff,
0x2400001e,
0x2400001e,
0x2305fbd1,
0x2305fdd1,
0x91983880,
0x10eeeee1,
0x24000061,
@ -1656,11 +1658,11 @@ const uint32_t Hiperface_DSL2_0_PRU_0[] = {
0x81100580,
0x240003c0,
0x810605c0,
0x24000a00,
0x24000b00,
0x810b1800,
0x81441800,
0x2eff8383,
0x2303999d,
0x23039b9d,
0x24000866,
0x2400000c,
0x2400002c,

2
source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h
View File

@ -1788,7 +1788,7 @@ const uint32_t Hiperface_DSL_SYNC2_0_PRU_0[] = {
0x81100580,
0x240003c0,
0x810605c0,
0x24000a00,
0x24000b00,
0x810b1800,
0x81441800,
0x2eff8383,

2
source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/.project/project_am243x.js
View File

@ -37,7 +37,7 @@ const defines = {
"PRU1",
"CHANNEL_0",
"ICSS_G_V_1_0",
"FREERUN_300_MHZ",
"SYNC_300_MHZ",
"HDSL_MULTICHANNEL",
"EXT_SYNC_ENABLE",
],

2
source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/.project/project_am64x.js
View File

@ -37,7 +37,7 @@ const defines = {
"PRU1",
"CHANNEL_0",
"ICSS_G_V_1_0",
"FREERUN_300_MHZ",
"SYNC_300_MHZ",
"HDSL_MULTICHANNEL",
"EXT_SYNC_ENABLE",
],

2
source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec
View File

@ -38,7 +38,7 @@
-DPRU1
-DCHANNEL_0
-DICSS_G_V_1_0
-DFREERUN_300_MHZ
-DSYNC_300_MHZ
-DHDSL_MULTICHANNEL
-DEXT_SYNC_ENABLE
"

4
source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile
View File

@ -56,7 +56,7 @@ ASM_SRCS__QUOTED += \
main.obj: ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES)
@echo 'Building file: "$<"'
@echo 'Invoking: PRU Compiler'
"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" $(GEN_OPTS__FLAG) "$<"
"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" $(GEN_OPTS__FLAG) "$<"
@echo 'Finished building: "$<"'
@echo ' '
@ -86,7 +86,7 @@ all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS)
hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS)
@echo 'Building target: "$@"'
@echo 'Invoking: PRU Linker'
"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.map" -i"$(CG_TOOL_ROOT)/lib" --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $(ORDERED_OBJS)
"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.map" -i"$(CG_TOOL_ROOT)/lib" --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $(ORDERED_OBJS)
@echo 'Finished building target: "$@"'
@echo ' '
@$(MAKE) --no-print-directory post-build

2
source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec
View File

@ -38,7 +38,7 @@
-DPRU1
-DCHANNEL_0
-DICSS_G_V_1_0
-DFREERUN_300_MHZ
-DSYNC_300_MHZ
-DHDSL_MULTICHANNEL
-DEXT_SYNC_ENABLE
"

4
source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile
View File

@ -56,7 +56,7 @@ ASM_SRCS__QUOTED += \
main.obj: ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES)
@echo 'Building file: "$<"'
@echo 'Invoking: PRU Compiler'
"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" $(GEN_OPTS__FLAG) "$<"
"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" $(GEN_OPTS__FLAG) "$<"
@echo 'Finished building: "$<"'
@echo ' '
@ -86,7 +86,7 @@ all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS)
hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS)
@echo 'Building target: "$@"'
@echo 'Invoking: PRU Linker'
"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.map" -i"$(CG_TOOL_ROOT)/lib" --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $(ORDERED_OBJS)
"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.map" -i"$(CG_TOOL_ROOT)/lib" --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $(ORDERED_OBJS)
@echo 'Finished building target: "$@"'
@echo ' '
@$(MAKE) --no-print-directory post-build

2
source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/.project/project_am243x.js
View File

@ -37,7 +37,7 @@ const defines = {
"PRU1",
"CHANNEL_1",
"ICSS_G_V_1_0",
"FREERUN_300_MHZ",
"SYNC_300_MHZ",
"HDSL_MULTICHANNEL",
"EXT_SYNC_ENABLE",
],

2
source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/.project/project_am64x.js
View File

@ -37,7 +37,7 @@ const defines = {
"PRU1",
"CHANNEL_1",
"ICSS_G_V_1_0",
"FREERUN_300_MHZ",
"SYNC_300_MHZ",
"HDSL_MULTICHANNEL",
"EXT_SYNC_ENABLE",
],

2
source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec
View File

@ -38,7 +38,7 @@
-DPRU1
-DCHANNEL_1
-DICSS_G_V_1_0
-DFREERUN_300_MHZ
-DSYNC_300_MHZ
-DHDSL_MULTICHANNEL
-DEXT_SYNC_ENABLE
"

4
source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile
View File

@ -56,7 +56,7 @@ ASM_SRCS__QUOTED += \
main.obj: ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES)
@echo 'Building file: "$<"'
@echo 'Invoking: PRU Compiler'
"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" $(GEN_OPTS__FLAG) "$<"
"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" $(GEN_OPTS__FLAG) "$<"
@echo 'Finished building: "$<"'
@echo ' '
@ -86,7 +86,7 @@ all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS)
hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS)
@echo 'Building target: "$@"'
@echo 'Invoking: PRU Linker'
"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.map" -i"$(CG_TOOL_ROOT)/lib" --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $(ORDERED_OBJS)
"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.map" -i"$(CG_TOOL_ROOT)/lib" --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $(ORDERED_OBJS)
@echo 'Finished building target: "$@"'
@echo ' '
@$(MAKE) --no-print-directory post-build

2
source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec
View File

@ -38,7 +38,7 @@
-DPRU1
-DCHANNEL_1
-DICSS_G_V_1_0
-DFREERUN_300_MHZ
-DSYNC_300_MHZ
-DHDSL_MULTICHANNEL
-DEXT_SYNC_ENABLE
"

4
source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile
View File

@ -56,7 +56,7 @@ ASM_SRCS__QUOTED += \
main.obj: ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES)
@echo 'Building file: "$<"'
@echo 'Invoking: PRU Compiler'
"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" $(GEN_OPTS__FLAG) "$<"
"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" $(GEN_OPTS__FLAG) "$<"
@echo 'Finished building: "$<"'
@echo ' '
@ -86,7 +86,7 @@ all: $(OBJS) $(CMD_SRCS) $(GEN_CMDS)
hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS)
@echo 'Building target: "$@"'
@echo 'Invoking: PRU Linker'
"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.map" -i"$(CG_TOOL_ROOT)/lib" --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $(ORDERED_OBJS)
"$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.map" -i"$(CG_TOOL_ROOT)/lib" --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $(ORDERED_OBJS)
@echo 'Finished building target: "$@"'
@echo ' '
@$(MAKE) --no-print-directory post-build