am64x/am243x: endat, sdfm: Update documentation
- Update design documentation for SDFM - Update features list for EnDat and SDFM - Update test cases description for EnDat - Update release notes and backward compatibility Fixes: PINDSW-6557 Signed-off-by: Achala Ram <a-ram@ti.com>
This commit is contained in:
Achala Ram
Dhaval Khandla
parent
4b0057b16e
commit
027f0c37b5
@ -10,14 +10,19 @@ ICSS %SDFM is a sigma delta interface for phase current measurement in high perf
|
||||
|
||||
## Features Supported
|
||||
- 3 %SDFM channels on single PRU core
|
||||
- Overcurrent (OC) for comparator: free running SINC3 filter with OSR 32-256
|
||||
- Normal current (NC) for data read: free running SINC3 filter with OSR 32-256, always multiple of OC OSR (NC OSR = K*OC OSR :: K ∈ Z)
|
||||
- Normal current (NC) for data read: SINC3 filter with OSR 16 to 256
|
||||
- Overcurrent (OC) for comparator: free running SINC3 filter with OSR 16 to 256
|
||||
- Event generation(ARM interrupt for data read from DMEM, GPIO toggle for high and low thresholds)
|
||||
- High and Low threshold comparator
|
||||
- Trigger based normal current sampling
|
||||
- Double update: Double normal current sampling per EPWM cycle
|
||||
- %SDFM Sync with EPWM
|
||||
|
||||
## Features Not Supported
|
||||
- Zero cross comparator
|
||||
- Below 32 OSR
|
||||
- OSR below 16
|
||||
- Clock phase compensation
|
||||
- Fast detect and trip generation
|
||||
|
||||
## ICSS SDFM Design
|
||||
\subpage SDFM_DESIGN explains the design in detail.
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# SDFM Interface Design {#SDFM_DESIGN}
|
||||
# %SDFM Interface Design {#SDFM_DESIGN}
|
||||
|
||||
[TOC]
|
||||
|
||||
@ -24,23 +24,23 @@ SDK example uses the %SDFM hardware capability in Slice 1 of PRU-ICSSG0.
|
||||
<table>
|
||||
<tr>
|
||||
<th>Parameter
|
||||
<th>Value
|
||||
<th>Default Value
|
||||
<th>Details
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Normal current OSR
|
||||
<td>32
|
||||
<td>Tested with 32, 64, 128 & 256
|
||||
<td>64
|
||||
<td>Tested with 16, 32, 64, 128 and 256
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Over current OSR
|
||||
<td>64
|
||||
<td>Tested with 32, 64, 128 & 256
|
||||
<td>16
|
||||
<td>Tested with 16, 32, 64, 128 and 256
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Sigma Delta Modulator Clock
|
||||
<td>20 MHz
|
||||
<td>
|
||||
<td> Tested with 5MHz, 10MHz and 20MHz from clock from PRU-ICSSG ECAP and 5MHz clock from SoC EPWM1
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Simulated EPWM frequency
|
||||
@ -49,42 +49,59 @@ SDK example uses the %SDFM hardware capability in Slice 1 of PRU-ICSSG0.
|
||||
</tr>
|
||||
<tr>
|
||||
<td>IEP frequency
|
||||
<td>300MHz
|
||||
<td>
|
||||
<td>300 MHz
|
||||
<td>Tested with 200MHz, 225MHz and 300MHz
|
||||
</tr>
|
||||
|
||||
</table>
|
||||
|
||||
### ICSS SDFM PRU hardware
|
||||
|
||||
Refer TRM for details
|
||||
Refer section 6.4.5.2.2.3.5 Sigma Delta (SD) Decimation Filtering in Technical Reference Manual(TRM) of AM243x for details.
|
||||
|
||||
### ICSS SDFM Firmware Implementation
|
||||
|
||||
Following section describes the firmware implementation of Sigma delta decimation filter on PRU-ICSS.
|
||||
Following section describes the firmware implementation of Sigma Delta Decimation Filter on PRU-ICSS.
|
||||
|
||||
#### Firmware Architecture
|
||||
|
||||
#### Firmware Architecture
|
||||
\image html SDFM_FIRMWARE_FLOWCHART.png "Overall Block Diagram"
|
||||
|
||||
Firmware first clear PRU registers & Task manager.
|
||||
Then it waits for the R5 to set %SDFM enable bit. After the enable set then it acknowledge to R5.
|
||||
After above these initial steps firmware does initialization of PRU-ICSSG's %SDFM hardware interface, task manager & IEP0 then it comes in infinite waiting loop.
|
||||
- Firmware first clears the PRU registers and task manager.
|
||||
- Then it waits for the ARM core to set %SDFM enable bit. After the enable bit is set, it sends an acknowledgement to ARM core.
|
||||
- After this, the firmware does initialization of PRU-ICSSG's %SDFM hardware interface, task manager and IEP0.
|
||||
- If threshold comparator is enabled, then a free run over current loop is setup, else it sets up an infinite waiting loop. In over current loop, the firmware reads sample data from the shadow copy register and does low and high theshold compersion with sample data, and depending on the configuration it toggles the GPIO pins.
|
||||
- Time triggered normal current task is configured to be triggered based on IEP CMP4 event. When the CMP4 event hits, the task manager sets the program counter to normal current task. In normal current task, firmware reads sample data from accumulator and it checks for fourth normal current sample (for SINC3 filtering). If the current normal current sample belongs to fourth normal current sample, then it stores the same in data memory DMEM as normal current row data and trigger interrupt.
|
||||
- At the end of normal current firmware task, execution flow comes into infinite waiting loop or over current loop.
|
||||
|
||||
When the COMP4 event hits the task manager assign OC loop to PC and Firmware starts execution of OC loop
|
||||
In OC loop firmware read sample data from accumulator and it checks for NC sample if the current OC sample belongs to NC sample then it does sampling for NC.
|
||||
During the NC sampling if current NC sample is closest to sample read time then it trigger R5 interrupt.
|
||||
at the end of OC loop firmware exit task manager and again firmware execution flow comes into infinite waiting loop.
|
||||
##### Normal Curent (NC)
|
||||
This section describes normal current implementation. Its implementation is trigger based. It starts execution when the trigger point is acquired (first time CMP4 event hits) and performs four continuous samplings to bring the accumulator and differntiator registers to stable state for the configured normal current OSR.
|
||||
|
||||
##### Threshold Comparator
|
||||
This section describe threshold comparator implementation. When the sample value crosses the high or low thresholds, the corresponding GPIO pin goes high.
|
||||
\image html Threshold_comparator_flow.png "Threshold Comparator"
|
||||
Initially the CMP4 register is configured with the first sample trigger start time and then until the next third continuous normal current sample it is updated with the normal current OSR sampling time. At the end of the fourth normal current sample again, it is updated with the second sample start time if double update is enabled otherwise with the first sample trigger start time.
|
||||
|
||||
\image html SDFM_NC_FLOW_CHART.png "Normal Current"
|
||||
|
||||
###### Single Update
|
||||
|
||||
##### Sample data read jitter
|
||||
Firmware trigger R5 interrupt for the NC sample closest to the sample read time in every PWM cycle.
|
||||
Normal current sampling is done per EPWM cycle.
|
||||
\image html SDFM_single_update.PNG "Single Update"
|
||||
|
||||
NOTE: There is some jitter in sample read timing, Sample data can be sampled before or after the maximum half nc sample time.
|
||||
###### Double Update
|
||||
|
||||
Normal current sampling is done twice in one EPWM cycle.
|
||||
|
||||
\image html SDFM_Double_update.PNG "Double Update"
|
||||
|
||||
##### Over Current (OC)/Threshold Comparator
|
||||
This section describes the over current implementation. It performs continuous sampling (free run) and when the sample value crosses the high or low threshold, the corresponding GPIO pin goes high.
|
||||
|
||||
\image html SDFM_OC_Flow_Chart.png "Over current"
|
||||
\image html SDFM_GPIO_toggle.png "GPIOs behaviour for High and Low threshold"
|
||||
|
||||
#### Sync with EPWM and trigger timing
|
||||
This section describes the EPWM to %SDFM synchronization and trigger timing for each EPWM cycle. At the end of the every EPWM cycle, the EPWM generates a sync out event that resets the IEP timer.
|
||||
The firmware initiates normal current sampling at the sample trigger point in each EPWM cycle. It takes four consecutive samples to bring the accumulator and differentiator registers to stable state. It takes the first sample at the trigger point and the next three samples, each after ONE_SAMPLE_TIME.
|
||||
Here ONE_SAMPLE_TIME is: OSR*(1/SD_CLK)
|
||||
\image html SDFM_epwm_sync_and_trigger_timing.png "Sync with EPWM and trigger timing"
|
||||
|
||||
#### AM64x/AM243x EVM Pin-Multiplexing
|
||||
<table>
|
||||
@ -141,16 +158,82 @@ NOTE: There is some jitter in sample read timing, Sample data can be sampled bef
|
||||
<tr>
|
||||
<td>PRG0_ECAP0_IN_APWM_OUT
|
||||
<td>PIN_PRG0_PRU1_GPO15
|
||||
<td>
|
||||
<td>ECAP output frequency
|
||||
</tr>
|
||||
<tr>
|
||||
<td>GPIO_MTR_1_PWM_EN
|
||||
<td>GPMC0_AD15/Y20
|
||||
<td>
|
||||
<td>Enable EPWM0 on 3-axis board
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SD8_CLK
|
||||
<td>PIN_PRG0_PRU0_GPO16
|
||||
<td>%SDFM clock input pin
|
||||
<td>Comman %SDFM clock input pin
|
||||
</tr>
|
||||
</table>
|
||||
</table>
|
||||
|
||||
\cond SOC_AM243X
|
||||
#### AM243x LP Pin-Multiplexing
|
||||
<table>
|
||||
<tr>
|
||||
<th>Pin name
|
||||
<th>Signal name
|
||||
<th>Function
|
||||
</tr>
|
||||
<tr>
|
||||
<td>GPIO_HIGH_TH_CH0
|
||||
<td>PRG1_PRU0_GPO18
|
||||
<td>(J7.64)Ch0 High threshold output
|
||||
</tr>
|
||||
<tr>
|
||||
<td>GPIO_LOW_TH_CH0
|
||||
<td>PRG0_PRU1_GPO11
|
||||
<td>(J7.70)Ch0 low threshold output
|
||||
</tr>
|
||||
<tr>
|
||||
<td>GPIO_HIGH_TH_CH1
|
||||
<td>PRG1_PRU0_GPO17
|
||||
<td>(J7.65)Ch1 High threshold output
|
||||
</tr>
|
||||
<tr>
|
||||
<td>GPIO_LOW_TH_CH1
|
||||
<td>PRG1_PRU0_GPO7
|
||||
<td>(J7.66)Ch1 low threshold output
|
||||
</tr>
|
||||
<tr>
|
||||
<td>GPIO_HIGH_TH_CH2
|
||||
<td>PRG0_PRU1_GPO1
|
||||
<td>(J7.67)Ch2 High threshold output
|
||||
</tr>
|
||||
<tr>
|
||||
<td>GPIO_LOW_TH_CH2
|
||||
<td>PRG0_PRU1_GPO2
|
||||
<td>(J7.68)Ch2 Low threshold output
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SD0_D
|
||||
<td>PIN_PRG0_PRU0_GPO1
|
||||
<td>(J4.32)Channel0 data input
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SD1_D
|
||||
<td>PIN_PRG0_PRU0_GPO3
|
||||
<td>(J2.19)Channel1 data input
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SD2_D
|
||||
<td>PIN_PRG0_PRU0_GPO5
|
||||
<td>(J2.13)Channel2 data input
|
||||
</tr>
|
||||
<tr>
|
||||
<td>PRG0_ECAP0_IN_APWM_OUT
|
||||
<td>PIN_PRG0_PRU1_GPO15
|
||||
<td>(J6.59)ECAP output frequency
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SD8_CLK
|
||||
<td>PIN_PRG0_PRU0_GPO16
|
||||
<td>(J1.7)Comman %SDFM clock input pin
|
||||
</tr>
|
||||
</table>
|
||||
\endcond
|
||||
@ -22,14 +22,14 @@ EnDat is a bidirectional interface for position encoders. During EnDat operation
|
||||
- Concurrent multi channel support (up-to 3 encoders with identical part number @ 8MHz maximum)
|
||||
- "Multi Channel with Encoders of Different Make" using load share mode (Each of PRU, RTU-PRU, and TX-PRU from one PRU-ICSSG slice handles one channel)
|
||||
- Safety Readiness: Recovery time
|
||||
- Clock up to 16MHz with single channel and load share mode (multi channel)
|
||||
|
||||
## Features Not Supported
|
||||
|
||||
In general, peripherals or features not mentioned as part of "Features Supported" section are not
|
||||
supported in this release, including the below
|
||||
- Safety
|
||||
- Clock configuration up to 16MHz
|
||||
- Independent clocks on multi channel mode.
|
||||
- Continuous clock mode in Multi-channel single PRU mode
|
||||
|
||||
## SysConfig Features
|
||||
|
||||
|
||||
@ -16,8 +16,11 @@
|
||||
Feature | Module
|
||||
------------------------------------------------------------------------------------------------|-----------------------------------
|
||||
SYNC Mode Support with 2 channels | Position Sense HDSL
|
||||
16 MHz EnDat clock frequency support | Position Sense EnDat
|
||||
Long cable support | Position Sense EnDat
|
||||
Trigger based normal current sampling | Current Sense %SDFM
|
||||
Double sampling per PWM cycle | Current Sense %SDFM
|
||||
Digital Control Library | Real Time Libraries
|
||||
|
||||
## Device and Validation Information
|
||||
|
||||
@ -63,16 +66,16 @@ Below features are not support on AM243X LAUNCHPAD due to SOC or board constrain
|
||||
|
||||
Module | Supported CPUs | SysConfig Support | OS Support | Key features tested | Key features not tested
|
||||
-------------|----------------|-------------------|-------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------|-----------------------------------------------------------------------------------
|
||||
EnDat | R5F | YES | FreeRTOS, NORTOS | Single channel, Multi channel, Continuous mode for single channel, Load share mode, Recovery Time for 2.2 command set, Boosterpack with AM243x-LP | 16 MHz Baud Rate Different cable lengths, Continuous clock mode for multi channel
|
||||
HDSL | R5F | YES | FreeRTOS, NORTOS | Freerun mode(300MHz,225MHz), Sync mode(225MHz), Short Message Read & Write, Long Message Read & Write, Boosterpack with AM243x-LP | Long cables
|
||||
Tamagawa | R5F | YES | FreeRTOS, NORTOS | Absolute position, Encoder ID, Reset, EEPROM Read, EEPROM Write, 2.5 Mbps and 5 Mbps Encoder Support, Boosterpack with AM243x-LP | -
|
||||
EnDat | R5F | YES | FreeRTOS, NORTOS | Single channel, Multi channel, Continuous mode for single channel, Load share mode, Recovery Time for 2.2 command set, Boosterpack with AM243x-LP | Encoder receive communication command
|
||||
HDSL | R5F | YES | FreeRTOS, NORTOS | Freerun mode(300MHz,225MHz), Sync mode(225MHz), Short Message Read & Write, Long Message Read & Write, Boosterpack with AM243x-LP | Long cables
|
||||
Tamagawa | R5F | YES | FreeRTOS, NORTOS | Absolute position, Encoder ID, Reset, EEPROM Read, EEPROM Write, 2.5 Mbps and 5 Mbps Encoder Support, Boosterpack with AM243x-LP | -
|
||||
|
||||
### Current Sense
|
||||
|
||||
|
||||
Module | Supported CPUs | SysConfig Support | OS Support | Key features tested | Key features not tested
|
||||
-------------|----------------|-------------------|-------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------|-----------------------------------------------------------------------------------
|
||||
%SDFM | R5F | YES | FreeRTOS, NORTOS | | -
|
||||
%SDFM | R5F | YES | FreeRTOS, NORTOS | 3 %SDFM channels on single PRU core, %SDFM Sync with EPWM, Overcurrent, single normal current sampling per PWM cycle, Double normal current sampling per PWM cycle, High and Low threshold comparator, Tested with SDFM clock from ECAP, Tested with 5MHz Clock from EPWM | -
|
||||
|
||||
|
||||
## Fixed Issues
|
||||
@ -181,6 +184,13 @@ Module | Supported CPUs | SysConfig Support | OS Support | Key feat
|
||||
<th> Applicable Releases
|
||||
<th> Workaround
|
||||
</tr>
|
||||
<tr>
|
||||
<td> PINDSW-5690
|
||||
<td> HDSL: EDGE register is not updated
|
||||
<td> Position Sense HDSL
|
||||
<td> 9.0 onwards
|
||||
<td> -
|
||||
</tr>
|
||||
<tr>
|
||||
<td> PINDSW-5537
|
||||
<td> HDSL not working with 225 MHz PRU-ICSSG Core Clock Frequency
|
||||
@ -189,22 +199,22 @@ Module | Supported CPUs | SysConfig Support | OS Support | Key feat
|
||||
<td> Use 300 MHz frequency for PRU-ICSSG Core Clock
|
||||
</tr>
|
||||
<tr>
|
||||
<td> PINDSW-6628
|
||||
<td> HDSL: Reset value of PRST bit is not correct
|
||||
<td> PINDSW-6486
|
||||
<td> HDSL: RSSI register shows higher values than expected for a non-noisy setup
|
||||
<td> Position Sense HDSL
|
||||
<td> 9.0 onwards
|
||||
<td> -
|
||||
</tr>
|
||||
<tr>
|
||||
<td> PINDSW-6608
|
||||
<td> PINDSW-6544
|
||||
<td> %SDFM: Incorrect samples seen intermittently with EPWM as %SDFM clock
|
||||
<td> Current Sense %SDFM
|
||||
<td> 9.0 onwards
|
||||
<td> -
|
||||
<td> Use 5MHz %SDFM clock from EPWM1 (tested with 5MHz clock from EPWM) or use PRU-ICSSG ECAP as %SDFM clock source
|
||||
</tr>
|
||||
<tr>
|
||||
<td> PINDSW-6630
|
||||
<td> HDSL: POS bit is not set during initial fast position alignment
|
||||
<td> PINDSW-6628
|
||||
<td> HDSL: Reset value of PRST bit is not correct
|
||||
<td> Position Sense HDSL
|
||||
<td> 9.0 onwards
|
||||
<td> -
|
||||
@ -217,15 +227,8 @@ Module | Supported CPUs | SysConfig Support | OS Support | Key feat
|
||||
<td> -
|
||||
</tr>
|
||||
<tr>
|
||||
<td> PINDSW-5690
|
||||
<td> HDSL: EDGE register is not updated
|
||||
<td> Position Sense HDSL
|
||||
<td> 9.0 onwards
|
||||
<td> -
|
||||
</tr>
|
||||
<tr>
|
||||
<td> PINDSW-6486
|
||||
<td> HDSL: RSSI register shows higher values than expected for a non-noisy setup
|
||||
<td> PINDSW-6630
|
||||
<td> HDSL: POS bit is not set during initial fast position alignment
|
||||
<td> Position Sense HDSL
|
||||
<td> 9.0 onwards
|
||||
<td> -
|
||||
@ -352,9 +355,9 @@ earlier SDKs.
|
||||
<th> Additional Remarks
|
||||
</tr>
|
||||
<tr>
|
||||
<td>
|
||||
<td>
|
||||
<td>
|
||||
<td> Current Sense %SDFM
|
||||
<td> Structure `SdfmPrms_s`
|
||||
<td> Added variables `iep_clock`, `sd_clock`, `en_second_update`, `firstSampTrigTime` and `secondSampTrigTime`
|
||||
<td>
|
||||
</tr>
|
||||
</table>
|
||||
@ -371,19 +374,55 @@ earlier SDKs.
|
||||
<tr>
|
||||
<td> Position Sense EnDat
|
||||
<td> \ref endat_init
|
||||
<td> Added api parameter
|
||||
<td> void* pruss_iep
|
||||
<td> Added API parameter `pruss_iep`
|
||||
<td> Needed for periodic mode
|
||||
</tr>
|
||||
<tr>
|
||||
<td> Position Sense EnDat
|
||||
<td> Structure: endat_priv
|
||||
<td> Added variables: pruss_iep, cmp3, cmp5 and cmp6
|
||||
<td>
|
||||
<td> Structure \ref endat_priv
|
||||
<td> Added variables `pruss_iep`, `cmp3`, `cmp5` and `cmp6`
|
||||
<td> Needed for periodic mode
|
||||
</tr>
|
||||
<tr>
|
||||
<td> Position Sense EnDat
|
||||
<td> Structure: cmd_supplement
|
||||
<td> Added variables: cmp3, cmp5 and cmp6
|
||||
<td>
|
||||
<td> Structure \ref cmd_supplement
|
||||
<td> Added variables `cmp3`, `cmp5` and `cmp6`
|
||||
<td> Needed for periodic mode
|
||||
</tr>
|
||||
<tr>
|
||||
<td> Current Sense %SDFM
|
||||
<td> `SDFM_setSampleReadingTime`
|
||||
<td> Changed name of API \ref SDFM_setSampleTriggerTime and updated a parameter name `samp_trig_time`
|
||||
<td> -
|
||||
</tr>
|
||||
<tr>
|
||||
<td> Current Sense %SDFM
|
||||
<td> \ref SDFM_setFilterOverSamplingRatio
|
||||
<td> Removed `oc_osr` parameter
|
||||
<td> -
|
||||
</tr>
|
||||
<tr>
|
||||
<td> Current Sense %SDFM
|
||||
<td> \ref SDFM_setCompFilterOverSamplingRatio
|
||||
<td> Changed type of osr parameter
|
||||
<td> uint8_t to uint16_t
|
||||
</tr>
|
||||
<tr>
|
||||
<td> Current Sense %SDFM
|
||||
<td> `SDFM_setAccOverSamplingRatio`
|
||||
<td> Removed this API
|
||||
<td> -
|
||||
</tr>
|
||||
<tr>
|
||||
<td> Current Sense %SDFM
|
||||
<td> Structure \ref SDFM_Ctrl
|
||||
<td> Removed variables: `ctrl` and `stat`, and added variables `sdfm_en`, `sdfm_en_ack` and `sdfm_pru_id`
|
||||
<td> -
|
||||
</tr>
|
||||
<tr>
|
||||
<td> Current Sense %SDFM
|
||||
<td> Structure \ref SDFM_CfgTrigger
|
||||
<td> Removed variables `trig_samp_time`, `oc_prd_iep_cnt` and `sample_count`, and added variables `en_double_nc_sampling`, `first_samp_trig_time` and `second_samp_trig_time`
|
||||
<td> -
|
||||
</tr>
|
||||
</table>
|
||||
|
||||
@ -652,7 +652,7 @@ Shown below is a sample output when the application is run:
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>2. Enter 10000 to select "clock frequency"</td>
|
||||
<td>2. Enter 1000 to select "clock frequency"</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
@ -692,7 +692,7 @@ Shown below is a sample output when the application is run:
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>2. Enter 0 to select channel 0(only for multi channel configuration) </td>
|
||||
<td>2. Enter 0 to select channel 0 </td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
@ -706,7 +706,7 @@ Shown below is a sample output when the application is run:
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>2. Enter 0 to select channel 0(only for multi channel configuration)</td>
|
||||
<td>2. Enter 0 to select channel 0</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
@ -720,7 +720,7 @@ Shown below is a sample output when the application is run:
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>2. Enter 10000 to select "clock frequency"</td>
|
||||
<td>2. Enter 1000 to select "clock frequency"</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
@ -734,7 +734,7 @@ Shown below is a sample output when the application is run:
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>2. Enter 0 to select channel 0(only for multi channel configuration)</td>
|
||||
<td>2. Enter 0 to select channel 0</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# SDFM {#EXAMPLE_MOTORCONTROL_SDFM}
|
||||
# %SDFM {#EXAMPLE_MOTORCONTROL_SDFM}
|
||||
|
||||
[TOC]
|
||||
|
||||
@ -10,10 +10,11 @@ The ICSS %SDFM example invokes these APIs to
|
||||
- Set %SDFM channels
|
||||
- Set ACC source, NC OSR, OC OSR, Clock source & Clock inversion
|
||||
- Enable & disable threshold comparators
|
||||
- Set high, low & zero cross threshold values
|
||||
- configure sample trigger time (time for read sample)
|
||||
- Set high and low threshold values
|
||||
- configure normal current sample trigger time (time for read sample)
|
||||
- Enable & disable double update
|
||||
- Inform firmware to enable %SDFM mode
|
||||
- Configure GPIO pins for high, low & zero cross thresholds
|
||||
- Configure GPIO pins for high and low threshold
|
||||
|
||||
|
||||
Once these steps are executed
|
||||
@ -31,9 +32,9 @@ Following section describes the Example implementation of ICSS %SDFM on ARM(R5F)
|
||||
<th>Folder/Files
|
||||
<th>Description
|
||||
</tr>
|
||||
<tr><td colspan="2" bgcolor=#F0F0F0> ${SDK_INSTALL_PATH}/examples/motor_control/icss_sdfm</td></tr>
|
||||
<tr><td colspan="2" bgcolor=#F0F0F0> ${SDK_INSTALL_PATH}/examples/current_sense/icss_sdfm</td></tr>
|
||||
<tr>
|
||||
<td>app_sddf.c & sddf.c</td>
|
||||
<td>app_sdfm.c & sdfm.c</td>
|
||||
<td>ICSS %SDFM application</td>
|
||||
</tr>
|
||||
<tr><td colspan="2" bgcolor=#F0F0F0> ${SDK_INSTALL_PATH}/source/current_sense/sdfm</td></tr>
|
||||
@ -45,6 +46,10 @@ Following section describes the Example implementation of ICSS %SDFM on ARM(R5F)
|
||||
<td>driver/</td>
|
||||
<td>ICSS %SDFM driver</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>include/</td>
|
||||
<td>Folder containing ICSS %SDFM structures & APIs sources</td>
|
||||
</tr>
|
||||
</table>
|
||||
|
||||
|
||||
@ -59,7 +64,7 @@ Following section describes the Example implementation of ICSS %SDFM on ARM(R5F)
|
||||
PRU | PRU0
|
||||
Toolchain | ti-arm-clang
|
||||
Board | @VAR_BOARD_NAME_LOWER
|
||||
Example folder | examples/motorcontrol/sddf
|
||||
Example folder | examples/current_sense/icss_sdfm
|
||||
|
||||
\endcond
|
||||
|
||||
@ -71,8 +76,8 @@ Following section describes the Example implementation of ICSS %SDFM on ARM(R5F)
|
||||
ICSSG | ICSSG0
|
||||
PRU | PRU0
|
||||
Toolchain | ti-arm-clang
|
||||
Board | @VAR_BOARD_NAME_LOWER
|
||||
Example folder | examples/motorcontrol/sddf
|
||||
Board | @VAR_BOARD_NAME_LOWER, @VAR_LP_BOARD_NAME_LOWER
|
||||
Example folder | examples/current_sense/icss_sdfm
|
||||
|
||||
\endcond
|
||||
|
||||
@ -84,9 +89,20 @@ Other than the basic EVM setup mentioned in \htmllink{@VAR_MCU_SDK_DOCS_PATH/EVM
|
||||
- Interface card connecting EVM and TIDEP-01015 3 Axis board
|
||||
- Signal generator
|
||||
|
||||
## Hardware Setup
|
||||
\image html SDFM_HwSetup_image.PNG "Hardware Setup SDFM"
|
||||
|
||||
### Hardware Setup
|
||||
\image html SDFM_HwSetup_image.PNG "Hardware Setup SDFM"
|
||||
\image html SDFM_EVM_HW_setup.png "SDFM: EVM and 3axis board setup view"
|
||||
\cond SOC_AM243X
|
||||
### Hardware Prerequisities for LP
|
||||
- AMC1035EVM
|
||||
- AM243x-LP board
|
||||
- Signal generator
|
||||
|
||||
#### LP Hardware set up
|
||||
\image html SDFM_LpHwSetup_image.png "LP Hardware setup"
|
||||
\image html SDFM_LpHwSetup.png "SDFM: LP setup view"
|
||||
\endcond
|
||||
## Build, load and run
|
||||
|
||||
- **When using CCS projects to build**, import the CCS project and build it using the CCS project menu (see \htmllink{@VAR_MCU_SDK_DOCS_PATH/CCS_PROJECTS_PAGE.html, Using SDK with CCS Projects}).
|
||||
@ -105,42 +121,80 @@ Other than the basic EVM setup mentioned in \htmllink{@VAR_MCU_SDK_DOCS_PATH/EVM
|
||||
<th>Pass/fail crieteria
|
||||
</tr>
|
||||
<tr>
|
||||
<td>To check raw data for 64 NC OSR</td>
|
||||
<td>1. Set NC OSR to 64</td>
|
||||
<td>Resolution of sampled data should be 13.9 bits </td>
|
||||
<td>1. Normal current sample data</td>
|
||||
<td>1. Run icss sdfm example on am64x/am243x board</td>
|
||||
<td>he drawn graph and raw data should look like the attached image</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>2. Set data read time half of epwm cycle</td>
|
||||
<td>2. Draw the graph of sdfm_ch0_samples, sdfm_ch1_samples and sdfm_ch2_samples arrays</td>
|
||||
<td>\image html SDFM_sample_output.PNG "NC sample data"</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>2. To check raw data for Single Update (64 NC OSR)</td>
|
||||
<td>1. Set NC OSR to 64</td>
|
||||
<td>The drawn graph and raw data should look like the attached image</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>2. Set single update trigger time to half of epwm cycle time </td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>3. Set epwm output frequency 20Khz</td>
|
||||
<td>3. Disable double update</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>3. Build and run icss sdfm example </td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>4. Draw graph for Raw data</td>
|
||||
<td>\image html SDFM_sample_output.PNG "NC sample data"</td>
|
||||
<td>\image html SDFM_Single_update_64OSR.PNG "Single Update Raw data"</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>To check raw data for 32 NC OSR</td>
|
||||
<td>1. Set NC OSR to 32</td>
|
||||
<td>Resolution of sampled data should be 11.4 bits </td>
|
||||
<td>3. To check Raw data for Double Update</td>
|
||||
<td>1. Set NC OSR to 64</td>
|
||||
<td>drawn Graphs and raw data should look like attached image</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>2. Set data read time half of epwm cycle</td>
|
||||
<td>2. Enable double update</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>3. Set single update trigger time to 1/4 of epwm cycle time</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>4. Set double update trigger time to 3/4 of epwm cycle time</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>3. Set epwm output frequency 20Khz</td>
|
||||
<td>5. Build and run icss sdfm example</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>6. Draw graph for Raw data</td>
|
||||
<td>\image html SDFM_Double_update_64OSR.PNG "Double Update Raw data"</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>To check Threshold comparator</td>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td>The pattern of the graph should be different from the single update graph. It takes 2 samples in one EPWM cycle so the graph pattern should look more like a sine wave compare to single update graph</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>4. To check Threshold comparator and Over current</td>
|
||||
<td>1. Set High Threshold to 3500 and low threshold to 2500</td>
|
||||
<td>Logic analyzer capture for High & Low Thresholds </td>
|
||||
</tr>
|
||||
@ -156,7 +210,89 @@ Other than the basic EVM setup mentioned in \htmllink{@VAR_MCU_SDK_DOCS_PATH/EVM
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>4. Capture signal in Logic analyzer</td>
|
||||
<td>4. Build and run icss sdfm example</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>5. Capture signal in Logic analyzer</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>5. To check NC Samples with Different NC OSR Values</td>
|
||||
<td>1. Set NC OSR values between 16 to 255 </td>
|
||||
<td>Raw data should have different resolution for different OSR values </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>2. Build and run icss sdfm example</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>3. Observe resolution of raw data</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>6. To check NC samples with different sdfm clock values</td>
|
||||
<td>1. Set NC OSR to 64</td>
|
||||
<td> Raw data should have different resolution for different sdfm clock values </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>2. Set ecap_divider variable in sdfm.c file for different sd clock generation</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>3. Set Sigma delta clock equal to ecap generated clock</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>4. Build and run example</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>5. Observe resolution of raw data</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
\cond SOC_AM243X
|
||||
<tr>
|
||||
<td>7.Testing with sdfm clock from EPWM </td>
|
||||
<td>1. Make hardware set up like attached image </td>
|
||||
<td>All test cases results should match with ECAP test case results</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>2. \image html SDFM_EPWM1_HW_Setup.png "SDFM: Hw set for clock from EPWM"</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>3. Enable "APP_EPWM1_ENABLE" macro in app_sdfm.c file</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>4. Set EPWM1 out put frequency to 12.5MHz or 5MHz in app_sdfm.c file</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>5. Set Sigma delta clock equal to EPWM1 output frequency</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>6. Build and run icss sdfm example</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>7. Test all tese cases from 1 to 5 with EPWM clock</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
\endcond
|
||||
</table>
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 111 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 68 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 464 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 458 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 468 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 350 KiB After Width: | Height: | Size: 480 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 53 KiB |
BIN
docs_src/docs/api_guide/images/current_sense/SDFM_LpHwSetup.png
Normal file
BIN
docs_src/docs/api_guide/images/current_sense/SDFM_LpHwSetup.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 456 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 692 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 478 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 474 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 77 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 465 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 11 KiB After Width: | Height: | Size: 52 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 55 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 271 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 218 KiB |
Loading…
Reference in New Issue
Block a user