2023-07-04 15:32:46 +03:00
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; Copyright (C) 2021-23 Texas Instruments Incorporated
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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;
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; Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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;
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; Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the
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; distribution.
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;
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; Neither the name of Texas Instruments Incorporated nor the names of
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; its contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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2023-09-13 15:02:41 +03:00
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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2023-07-04 15:32:46 +03:00
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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;offsets for ch0 (without loadshare mode use these ch0 offset for all three channels)
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ENDAT_CH0_OPMODE_CONFIG_OFFSET .set 0x0 ; 0: PRU trigger 1: Host trigger
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ENDAT_CH0_CHANNEL_CONFIG_OFFSET .set 0x1 ; Select single channel (1, 2, 3 or Multi (0))- Not implemented yet
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ENDAT_CH0_INTFC_CMD_TRIGGER_OFFSET .set 0x2 ; Command trigger indication to firmware
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ENDAT_CH0_INTFC_CMD_STATUS_OFFSET .set 0x3 ; Status word for channel busy indication etc - Not used now
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;offsets for ch1 with loadshare mode, without loadshare mode no use for this offset configuration
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ENDAT_CH1_OPMODE_CONFIG_OFFSET .set 0x4 ; 0: PRU trigger 1: Host trigger
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ENDAT_CH1_CHANNEL_CONFIG_OFFSET .set 0x5 ; Select single channel 1
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ENDAT_CH1_INTFC_CMD_TRIGGER_OFFSET .set 0x6 ; Command trigger indication to firmware
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ENDAT_CH1_INTFC_CMD_STATUS_OFFSET .set 0x7 ; Status word for channel busy indication etc - Not used now
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;offsets for ch2 with loadshare mode,
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ENDAT_CH2_OPMODE_CONFIG_OFFSET .set 0x8 ; 0: PRU trigger 1: Host trigger
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ENDAT_CH2_CHANNEL_CONFIG_OFFSET .set 0x9 ; Select single channel 2
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ENDAT_CH2_INTFC_CMD_TRIGGER_OFFSET .set 0xA ; Command trigger indication to firmware
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ENDAT_CH2_INTFC_CMD_STATUS_OFFSET .set 0xB ; Status word for channel busy indication etc - Not used now
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;Command offset for ch0 and (command offset for all three channels in without load share mode)
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ENDAT_CH0_CMD_WORD_0_OFFSET .set 0xC ; Command parameters for firmware
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ENDAT_CH0_CMD_WORD_0_CMDNADDR_OFFSET .set 0xC ; 1-bit dummy + 6-bits command mode + 9 bits (address + 1-bit param)
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ENDAT_CH0_CMD_WORD_0_PARAM_OFFSET .set 0xE ; 15-bit params
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ENDAT_CH0_CMD_WORD_1_OFFSET .set 0x10 ; Command parameters for firmware
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ENDAT_CH0_CMD_WORD_1_RXBITS_OFFSET .set 0x10 ; Number of bits to receive in command response for ch1
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ENDAT_CH0_CMD_WORD_1_TXBITS_OFFSET .set 0x11 ; Number of bits to transmit to encoder
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ENDAT_CH0_CMD_WORD_1_CMDTYP_OFFSET .set 0x12 ; 0: EnDat2.2 otherwise: EnDat2.1 or ENDAT_CMD_SEND_POSVAL_WITH_DATA
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ENDAT_CH0_CMD_WORD_1_BLKLEN_OFFSET .set 0x13 ; Block address length in bytes, 0 if not present
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ENDAT_CH0_CMD_WORD_2_OFFSET .set 0x14 ; Command parameters for firmware - 2.2 command supplement
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ENDAT_CH0_CMD_WORD_2_ADDR_OFFSET .set 0x14 ; 8-bit address
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ENDAT_CH0_CMD_WORD_2_PARAM_OFFSET .set 0x15 ; 16-bit data
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ENDAT_CH0_CMD_WORD_2_BLKADDR_OFFSET .set 0x17 ; 8-bit optional block address
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;Command offset for ch1, use only with loadshare
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ENDAT_CH1_CMD_WORD_0_OFFSET .set 0x18 ; Command parameters for firmware
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ENDAT_CH1_CMD_WORD_0_CMDNADDR_OFFSET .set 0x18 ; 1-bit dummy + 6-bits command mode + 9 bits (address + 1-bit param)
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ENDAT_CH1_CMD_WORD_0_PARAM_OFFSET .set 0x1A ; 15-bit params
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ENDAT_CH1_CMD_WORD_1_OFFSET .set 0x1C ; Command parameters for firmware
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ENDAT_CH1_CMD_WORD_1_RXBITS_OFFSET .set 0x1C ; Number of bits to receive in command response for ch1
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ENDAT_CH1_CMD_WORD_1_TXBITS_OFFSET .set 0x1D ; Number of bits to transmit to encoder
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ENDAT_CH1_CMD_WORD_1_CMDTYP_OFFSET .set 0x1E ; 0: EnDat2.2 otherwise: EnDat2.1 or ENDAT_CMD_SEND_POSVAL_WITH_DATA
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ENDAT_CH1_CMD_WORD_1_BLKLEN_OFFSET .set 0x1F ; Block address length in bytes, 0 if not present
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ENDAT_CH1_CMD_WORD_2_OFFSET .set 0x20 ; Command parameters for firmware - 2.2 command supplement
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ENDAT_CH1_CMD_WORD_2_ADDR_OFFSET .set 0x20 ; 8-bit address
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ENDAT_CH1_CMD_WORD_2_PARAM_OFFSET .set 0x21 ; 16-bit data
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ENDAT_CH1_CMD_WORD_2_BLKADDR_OFFSET .set 0x23 ; 8-bit optional block address
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;Command offset for ch2, use only with loadshare
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ENDAT_CH2_CMD_WORD_0_OFFSET .set 0x24 ; Command parameters for firmware
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ENDAT_CH2_CMD_WORD_0_CMDNADDR_OFFSET .set 0x24 ; 1-bit dummy + 6-bits command mode + 9 bits (address + 1-bit param)
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ENDAT_CH2_CMD_WORD_0_PARAM_OFFSET .set 0x26 ; 15-bit params
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ENDAT_CH2_CMD_WORD_1_OFFSET .set 0x28 ; Command parameters for firmware
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ENDAT_CH2_CMD_WORD_1_RXBITS_OFFSET .set 0x28 ; Number of bits to receive in command response for ch1
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ENDAT_CH2_CMD_WORD_1_TXBITS_OFFSET .set 0x29 ; Number of bits to transmit to encoder
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ENDAT_CH2_CMD_WORD_1_CMDTYP_OFFSET .set 0x2A ; 0: EnDat2.2 otherwise: EnDat2.1 or ENDAT_CMD_SEND_POSVAL_WITH_DATA
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ENDAT_CH2_CMD_WORD_1_BLKLEN_OFFSET .set 0x2B ; Block address length in bytes, 0 if not present
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ENDAT_CH2_CMD_WORD_2_OFFSET .set 0x2C ; Command parameters for firmware - 2.2 command supplement
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ENDAT_CH2_CMD_WORD_2_ADDR_OFFSET .set 0x2C ; 8-bit address
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ENDAT_CH2_CMD_WORD_2_PARAM_OFFSET .set 0x2D ; 16-bit data
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ENDAT_CH2_CMD_WORD_2_BLKADDR_OFFSET .set 0x2F ; 8-bit optional block address
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2023-10-19 08:32:56 +03:00
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;;;;;;;;;;;;; EnDat Channel info offset ;;;;;;;;;;;;;;;;;;;;;
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;CH0 registers
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ENDAT_CH0_NUM_CLOCK_PULSES_OFFSET .set 0X30
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ENDAT_CH0_ENDAT22_STAT_OFFSET .set 0x31
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ENDAT_CH0_CLOCK_LESS_FOR_TD .set 0x32
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ENDAT_CH0_MEAS_PROPDELAY_OFFSET .set 0x34
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ENDAT_CH0_CRC_ERR_COUNTER_OFFSET .set 0X38 ; CRC error count
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;CH1 registers
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ENDAT_CH1_NUM_CLOCK_PULSES_OFFSET .set 0x40
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ENDAT_CH1_ENDAT22_STAT_OFFSET .set 0x41
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ENDAT_CH1_CLOCK_LESS_FOR_TD .set 0x42
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ENDAT_CH1_MEAS_PROPDELAY_OFFSET .set 0x44
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ENDAT_CH1_CRC_ERR_COUNTER_OFFSET .set 0x48 ; CRC error count
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;CH2 registers
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ENDAT_CH2_NUM_CLOCK_PULSES_OFFSET .set 0x50
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ENDAT_CH2_ENDAT22_STAT_OFFSET .set 0x51
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ENDAT_CH2_CLOCK_LESS_FOR_TD .set 0x52
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ENDAT_CH2_MEAS_PROPDELAY_OFFSET .set 0x54
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ENDAT_CH2_CRC_ERR_COUNTER_OFFSET .set 0x58 ; CRC error count
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;;;;;;;;;;Configured memory address offset ;;;;;;;;;;;
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ENDAT_CONFIG_CH_INFO_MEMORY_ADDRESS .set 0x60 ;64 bit data store memory address
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;;;;;;;;;; clock configuration ;;;;;;;;;
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ENDAT_CONFIG_CLOCK_RX_OFFSET .set 0x68 ; clock to be configure for rx = tx * oversample rate
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ENDAT_CONFIG_CLOCK_TX_OFFSET .set 0x6A ; clock to be configure for tx
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ENDAT_CONFIG_CLOCK_RX_EN_CNT_OFFSET .set 0x6C ; rx arm delay
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2023-07-04 15:32:46 +03:00
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2023-10-19 08:32:56 +03:00
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; Delay Configuration
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ENDAT_CONFIG_DELAY_125NS_OFFSET .set 0x70
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ENDAT_CONFIG_DELAY_5US_OFFSET .set 0x74
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ENDAT_CONFIG_DELAY_51US_OFFSET .set 0x78
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ENDAT_CONFIG_DELAY_1MS_OFFSET .set 0x7C
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ENDAT_CONFIG_DELAY_2MS_OFFSET .set 0x80 ; delay for 2ms counter
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ENDAT_CONFIG_DELAY_12MS_OFFSET .set 0x84 ; delay for 12ms counter
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ENDAT_CONFIG_DELAY_50MS_OFFSET .set 0x88 ; delay for 20ms counter
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ENDAT_CONFIG_DELAY_380MS_OFFSET .set 0x8C
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ENDAT_CONFIG_DELAY_900MS_OFFSET .set 0X90
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;;;;;;;;; mask for core set ;;;;;;;;
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MASK_FOR_PRIMARY_CORE .set 0x94
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;rx complete status
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ENDAT_CH0_CONFIG_SYN_BIT .set 0x95 ;0th bit for ch0
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ENDAT_CH1_CONFIG_SYN_BIT .set 0x96 ;0th bit for ch0
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ENDAT_CH2_CONFIG_SYN_BIT .set 0x97 ;0th bit for ch0
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;;;;;;; icssgclock ;;;;;;;;;;;;;;
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PRUICSSG_CLOCK .set 0x98;
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;;;;;;;;;; EnDat channel Rx info offset ;;;;;;;;
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2023-07-04 15:32:46 +03:00
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; NOTE: For ENDAT_CHx_POSITION_DATA_LSW_OFFSET: Bit0 is Error flag (EnDat2.1) and Bit0,Bit1 are Error flags (EnDat2.2)
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; CH0 registers
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2023-10-19 08:32:56 +03:00
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ENDAT_CH0_POSITION_DATA_WORD0_OFFSET .set 0x00
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ENDAT_CH0_POSITION_DATA_WORD1_OFFSET .set 0x04
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ENDAT_CH0_POSITION_DATA_WORD2_OFFSET .set 0x08
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ENDAT_CH0_POSITION_DATA_WORD3_OFFSET .set 0x0C
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ENDAT_CH0_CRC_STATUS_OFFSET .set 0x10
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ENDAT_CH0_RT_OFFSET .set 0x14
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2023-07-04 15:32:46 +03:00
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; CH1 registers
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2023-10-19 08:32:56 +03:00
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ENDAT_CH1_POSITION_DATA_WORD0_OFFSET .set 0x18
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ENDAT_CH1_POSITION_DATA_WORD1_OFFSET .set 0x1C
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ENDAT_CH1_POSITION_DATA_WORD2_OFFSET .set 0x20
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ENDAT_CH1_POSITION_DATA_WORD3_OFFSET .set 0X24
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ENDAT_CH1_CRC_STATUS_OFFSET .set 0x28
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ENDAT_CH1_RT_OFFSET .set 0x2C
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2023-07-04 15:32:46 +03:00
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; CH2 registers
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2023-10-19 08:32:56 +03:00
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ENDAT_CH2_POSITION_DATA_WORD0_OFFSET .set 0x30
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ENDAT_CH2_POSITION_DATA_WORD1_OFFSET .set 0x34
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ENDAT_CH2_POSITION_DATA_WORD2_OFFSET .set 0x38
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ENDAT_CH2_POSITION_DATA_WORD3_OFFSET .set 0x3C
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ENDAT_CH2_CRC_STATUS_OFFSET .set 0x40
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ENDAT_CH2_RT_OFFSET .set 0x44
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2023-08-22 16:46:42 +03:00
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