2023-07-04 15:32:46 +03:00
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; Copyright (C) 2021-2023 Texas Instruments Incorporated
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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;
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; Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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;
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; Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the
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; distribution.
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;
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; Neither the name of Texas Instruments Incorporated nor the names of
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; its contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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2023-09-13 15:02:41 +03:00
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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2023-07-04 15:32:46 +03:00
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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.include "memory.inc"
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.include "defines.inc"
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.include "macros.inc"
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.sect ".text"
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.global update_events
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.global demp_data_symbols
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.global calc_acc_crc
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.global calc_16bit_crc
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.global load_code
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;--------------------------------------------------------------------------------------------------
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;Function: update_events (RET_ADDR1)
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;Updates event register and generates interrupts if necessary
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; 9 cycles
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;input:
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; REG_FNC.b0: event number
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;output:
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;modifies:
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;--------------------------------------------------------------------------------------------------
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update_events:
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;read events and masks
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lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 4
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set REG_TMP0.w0, REG_TMP0.w0, REG_FNC.b0
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;save events
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sbco ®_TMP0.w0, MASTER_REGS_CONST, EVENT_H, 2
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qbbc update_events_no_int, REG_TMP0.w2, REG_FNC.b0
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;generate interrupt
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ldi r31.w0, PRU0_ARM_IRQ
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update_events_no_int:
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RET1
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;--------------------------------------------------------------------------------------------------
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;Function: calc_16bit_crc (RET_ADD1)
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;This function checks the crc for the acceleration channel (polynomial is x^5 + x^2 + 1)
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;11*REG_FNC.b2+3 cycles -> 69 cycles for 6 bytes data
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;input:
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; REG_FNC.b0: num bytes
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; r1.b0: pointer to register + 1 byte, counting down from there
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;output:
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; REG_FNC.w0: 16 bit CRC
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;modifies:
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; REG_TMP0, REG_FNC, r1
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;--------------------------------------------------------------------------------------------------
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calc_16bit_crc:
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ldi REG_TMP2, (LUT_CRC16+PDMEM00)
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mov REG_TMP0.b2, REG_FNC.b0
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ldi REG_FNC.w0, 0
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calc_16bit_crc_loop:
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ldi REG_TMP0.w0, 0
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mvib REG_TMP0.b0, *--r1.b0
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xor REG_TMP0.b0, REG_FNC.b1, REG_TMP0.b0
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lsl REG_TMP0.w0, REG_TMP0.w0, 1
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lbbo ®_TMP0.w0, REG_TMP2, REG_TMP0.w0, 2
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lsl REG_FNC.w0, REG_FNC.w0, 8
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xor REG_FNC.w0, REG_TMP0.w0, REG_FNC.w0
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sub REG_TMP0.b2, REG_TMP0.b2, 1
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qblt calc_16bit_crc_loop, REG_TMP0.b2, 0
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;CRC_L is flipped
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xor REG_FNC.b0, REG_FNC.b0, 0xff
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RET1
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