267 lines
10 KiB
Plaintext
267 lines
10 KiB
Plaintext
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%%{
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let options = args.options;
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let stackSize = 16*1024;
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let heapSize = 32*1024;
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/* with nested interrupts logic added, IRQ stack is only used minimally, instead
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* SVC stack is used, hence IRQ stack size is less as compared to SVC stack
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*/
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let irqStackSize = 256;
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let svcStackSize = 4*1024;
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let fiqStackSize = 256;
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let abortStackSize = 256;
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let undefinedStackSize = 256;
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let codeDataAddr = 0;
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let codeDataSize = 0;
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let codeDataAddrFlash = 0;
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let codeDataSizeFlash = 0;
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let useFlash = false;
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let addrBase = 0;
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let addrBaseFlash = 0;
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let isSingleCore = false;
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/* Temp change till we support DDR - alloc all memory to single core
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* as we don't plan to run code coverage for system project */
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if(args.isInstrumentation)
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{
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isSingleCore = true;
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}
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let isIcssPktBufEnable = false;
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if(options && options.isXip)
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{
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useFlash = true;
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}
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/* if no options given use defaults */
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if(options && options.stackSize)
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stackSize = options.stackSize;
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if(options && options.heapSize)
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heapSize = options.heapSize;
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if(options && options.irqStackSize)
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irqStackSize = options.irqStackSize;
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if(options && options.fiqStackSize)
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fiqStackSize = options.fiqStackSize;
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if(options && options.svcStackSize)
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svcStackSize = options.svcStackSize;
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if(options && options.abortStackSize)
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abortStackSize = options.abortStackSize;
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if(options && options.undefinedStackSize)
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undefinedStackSize = options.undefinedStackSize;
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if(options && options.isSingleCore)
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isSingleCore = options.isSingleCore;
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if(options && options.isIcssPktBufEnable)
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isIcssPktBufEnable = options.isIcssPktBufEnable;
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if(isSingleCore === true) {
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codeDataSize = 0x40000 * 4;
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codeDataSizeFlash = 0x80000;
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}
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else {
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codeDataSize = 0x40000;
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codeDataSizeFlash = 0x80000;
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}
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/* MSS mailbox memory */
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let ipcShmAddrBase = 0x72000000;
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/* offset from top of codeDataAddrDdr where the code/data is actually placed,
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the first codeDataOffsetDdr bytes are used for IPC in linux
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*/
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addrBase = 0x70040000;
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addrBaseFlash = 0x60100000;
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if(isSingleCore === true) {
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codeDataAddr = addrBase;
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codeDataAddrFlash = addrBaseFlash;
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}
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else {
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if(args.project.cpu == "r5fss0-0") {
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codeDataAddr = addrBase + codeDataSize*0;
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codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*0;
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}
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if(args.project.cpu == "r5fss0-1") {
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codeDataAddr = addrBase + codeDataSize*1;
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codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*1;
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}
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if(args.project.cpu == "r5fss1-0") {
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codeDataAddr = addrBase + codeDataSize*2;
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codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*2;
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}
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if(args.project.cpu == "r5fss1-1") {
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codeDataAddr = addrBase + codeDataSize*3;
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codeDataAddrFlash = addrBaseFlash + codeDataSizeFlash*3;
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}
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}
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if(options && options.codeDataAddr)
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codeDataAddr = options.codeDataAddr;
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if(options && options.codeDataSize)
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codeDataSize = options.codeDataSize;
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if(options && options.codeDataAddrFlash)
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codeDataAddrFlash = options.codeDataAddrFlash;
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if(options && options.codeDataSizeFlash)
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codeDataSizeFlash = options.codeDataSizeFlash;
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%%}
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/* This is the stack that is used by code running within main()
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* In case of NORTOS,
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* - This means all the code outside of ISR uses this stack
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* In case of FreeRTOS
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* - This means all the code until vTaskStartScheduler() is called in main()
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* uses this stack.
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* - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
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*/
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--stack_size=`stackSize`
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/* This is the heap size for malloc() API in NORTOS and FreeRTOS
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* This is also the heap used by pvPortMalloc in FreeRTOS
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*/
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--heap_size=`heapSize`
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-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
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/* This is the size of stack when R5 is in IRQ mode
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* In NORTOS,
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* - Here interrupt nesting is enabled
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* - This is the stack used by ISRs registered as type IRQ
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* In FreeRTOS,
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* - Here interrupt nesting is enabled
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* - This is stack that is used initally when a IRQ is received
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* - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
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* - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
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*/
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__IRQ_STACK_SIZE = `irqStackSize`;
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/* This is the size of stack when R5 is in IRQ mode
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* - In both NORTOS and FreeRTOS nesting is disabled for FIQ
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*/
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__FIQ_STACK_SIZE = `fiqStackSize`;
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__SVC_STACK_SIZE = `svcStackSize`; /* This is the size of stack when R5 is in SVC mode */
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__ABORT_STACK_SIZE = `abortStackSize`; /* This is the size of stack when R5 is in ABORT mode */
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__UNDEFINED_STACK_SIZE = `undefinedStackSize`; /* This is the size of stack when R5 is in UNDEF mode */
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SECTIONS
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{
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/* This has the R5F entry point and vector table, this MUST be at 0x0 */
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.vectors:{} palign(8) > R5F_VECS
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/* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000
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* i.e this cannot be placed in DDR
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*/
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GROUP {
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.text.hwi: palign(8)
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.text.cache: palign(8)
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.text.mpu: palign(8)
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.text.boot: palign(8)
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.text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
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} > OCRAM
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/* This is rest of code. This can be placed in DDR if DDR is available and needed */
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GROUP {
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.text: {} palign(8) /* This is where code resides */
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.rodata: {} palign(8) /* This is where const's go */
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% if(useFlash) {
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} > FLASH
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% } else {
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} > OCRAM
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% }
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/* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
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GROUP {
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.data: {} palign(8) /* This is where initialized globals and static go */
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} > OCRAM
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/* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
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GROUP {
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.bss: {} palign(8) /* This is where uninitialized globals go */
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RUN_START(__BSS_START)
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RUN_END(__BSS_END)
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.sysmem: {} palign(8) /* This is where the malloc heap goes */
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.stack: {} palign(8) /* This is where the main() stack goes */
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} > OCRAM
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% if(args.isInstrumentation) {
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GROUP {
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__llvm_prf_cnts: {} align(8)
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RUN_START(__start___llvm_prf_cnts)
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RUN_END(__stop___llvm_prf_cnts)
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} > OCRAM
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% }
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/* This is where the stacks for different R5F modes go */
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GROUP {
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.irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
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RUN_START(__IRQ_STACK_START)
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RUN_END(__IRQ_STACK_END)
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.fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
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RUN_START(__FIQ_STACK_START)
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RUN_END(__FIQ_STACK_END)
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.svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
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RUN_START(__SVC_STACK_START)
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RUN_END(__SVC_STACK_END)
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.abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
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RUN_START(__ABORT_STACK_START)
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RUN_END(__ABORT_STACK_END)
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.undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
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RUN_START(__UNDEFINED_STACK_START)
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RUN_END(__UNDEFINED_STACK_END)
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} > OCRAM
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/* Sections needed for C++ projects */
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GROUP {
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.ARM.exidx: {} palign(8) /* Needed for C++ exception handling */
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.init_array: {} palign(8) /* Contains function pointers called before main */
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.fini_array: {} palign(8) /* Contains function pointers called after main */
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% if(useFlash) {
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} > FLASH
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% } else {
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} > OCRAM
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% }
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% if (isIcssPktBufEnable) {
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/* Packet buffer memory used by ICCS */
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.bss.icss_emac_pktbuf_mem (NOLOAD): {} > ICSS_PKT_BUF_MEM
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% }
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/* General purpose user shared memory, used in some examples */
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.bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
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/* this is used when Debug log's to shared memory are enabled, else this is not used */
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.bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM
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/* this is used only when IPC RPMessage is enabled, else this is not used */
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.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
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/* this is used only when Secure IPC is enabled */
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.bss.sipc_hsm_queue_mem (NOLOAD) : {} > MAILBOX_HSM
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.bss.sipc_r5f_queue_mem (NOLOAD) : {} > MAILBOX_R5F
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}
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MEMORY
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{
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R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040
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R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
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R5F_TCMB : ORIGIN = 0x00080000 , LENGTH = 0x00008000
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/* when using multi-core application's i.e more than one R5F/M4F active, make sure
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* this memory does not overlap with other R5F's
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*/
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OCRAM : ORIGIN = 0x`codeDataAddr.toString(16).toUpperCase()` , LENGTH = 0x`codeDataSize.toString(16).toUpperCase()`
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/* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
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* other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
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*/
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FLASH : ORIGIN = 0x`codeDataAddrFlash.toString(16).toUpperCase()` , LENGTH = 0x`codeDataSizeFlash.toString(16).toUpperCase()`
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% if (isIcssPktBufEnable) {
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/* shared memories that is used between ICCS and this core. MARK as non-cache or cache+sharable */
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ICSS_PKT_BUF_MEM : ORIGIN = 0x70000000, LENGTH = 0x00010000
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% }
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/* shared memories that are used by RTOS/NORTOS cores */
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/* On R5F,
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* - make sure there is a MPU entry which maps below regions as non-cache
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*/
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USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x00004000
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LOG_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x00004000
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/* MSS mailbox memory is used as shared memory, we dont use bottom 32*12 bytes, since its used as SW queue by ipc_notify */
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RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x`ipcShmAddrBase.toString(16).toUpperCase()`, LENGTH = 0x3E80
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MAILBOX_HSM: ORIGIN = 0x44000000 , LENGTH = 0x000003CE
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MAILBOX_R5F: ORIGIN = 0x44000400 , LENGTH = 0x000003CE
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}
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