2023-12-01 09:30:39 +03:00
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/*
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* Copyright (C) 2023 Texas Instruments Incorporated
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef BISSC_INTERFACE_H_
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#define BISSC_INTERFACE_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ========================================================================== */
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/* Macros */
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/* ========================================================================== */
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/* ========================================================================== */
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/* Structures */
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/* ========================================================================== */
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/**
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* \brief Structure defining BiSSC Raw data received from encoder.
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*
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*/
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2023-12-14 15:35:14 +03:00
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struct raw_data
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{
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2023-12-01 09:30:39 +03:00
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volatile uint32_t pos_data_word0;
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/**< Initial (<=32) position bits received */
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volatile uint32_t pos_data_word1;
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/**< position bits received after the initial 32 bits (if applicable) */
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};
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/**
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* \brief Structure defining BiSSC Position data lengths of conected encoder.
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*
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2023-12-14 15:35:14 +03:00
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* \details Number of encoders connected in daisy chain, and their position data lengths(resolution).
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*/
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2023-12-14 15:35:14 +03:00
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struct enc_len
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{
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volatile uint8_t num_encoders;
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2023-12-01 09:30:39 +03:00
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/**< Number of Encoders connected */
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volatile uint8_t data_len[3];
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/**< Data length of individual encoder connected in daisy chain*/
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};
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/**
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* \brief Structure defining BiSSC Position data results.
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*
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* \details raw data, position data crc error count, 6-bit otf crc.
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*/
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2023-12-14 15:35:14 +03:00
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struct pos_data_res
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{
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struct raw_data raw_data[3];
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/**< Structure defining BiSSC Raw data received from encoder*/
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volatile uint32_t pd_crc_err_cnt[3];
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/**< Position data CRC error count */
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volatile uint8_t pos_data_otf_crc[3];
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/**< position data otf crc bits*/
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};
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/**
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* \brief Structure defining BiSSC Channel specific control communication(ctrl) results
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*
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* \details ctrl crc error count,cds results, ctrl 4 bit received crc and ctrl otf crc.
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*
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*/
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struct ctrl_res
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{
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volatile uint32_t ctrl_crc_err_cnt;
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/**< control communication CRC error count */
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volatile uint8_t ctrl_cds_res;
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/**< control communication result*/
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volatile uint8_t ctrl_rcvd_crc;
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/**< control communication crc received*/
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volatile uint8_t ctrl_otf_crc;
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/**< control communication otf crc computed*/
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};
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/**
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* \brief Structure defining BiSSC interface
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*
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* \details Firmware config, command and channel interface
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*
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*/
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struct bissc_pruicss_xchg
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{
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volatile uint8_t pos_crc_len;
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/**< Position data CRC length */
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volatile uint8_t rx_clk_freq;
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/**< Clock frequency */
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volatile uint8_t ctrl_cmd_crc_len;
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/**< Control command CRC length */
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volatile uint8_t channel;
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/**< Channel configuration */
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volatile uint8_t status[3];
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/**< Firmware initialization status */
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volatile uint8_t primary_core_mask;
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/**< Primary core mask incase of load share */
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volatile uint8_t cycle_trigger[3];
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/**< BiSSC cycle complete status */
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volatile uint8_t measure_proc_delay;
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/**< measure processing delay - do this for every config change */
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struct enc_len enc_len[3];
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/**< position data lengths(resolution) of BiSSC encoders connected */
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volatile uint8_t valid_bit_idx;
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/**< channel Bit Index */
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volatile uint8_t fifo_bit_idx;
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/**< Fifo Bit Index(middle bit) */
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volatile uint8_t ctrl_cmd_status[3];
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/**< control communication status */
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volatile uint16_t proc_delay[3];
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/**< automatically estimated processing delay */
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volatile uint32_t ctrl_cmd[3];
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/**< Hex equivalent Control command */
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volatile uint32_t max_proc_delay;
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/**< maximum processing delay for selected frequency */
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struct pos_data_res pos_data_res[3];
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/**< Channel specific position data results*/
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struct ctrl_res ctrl_res[3];
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/**< Channel specific control communication results*/
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volatile uint8_t execution_state[3];
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/**< Execution state for different channels in load share */
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volatile uint64_t register_backup[3];
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/**< Backup registers for ch0 - ch2 */
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volatile uint8_t bissc_re_measure_proc_delay;
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volatile uint32_t delay_40us;
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/**< BiSS-C Timeout delay */
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volatile uint32_t delay_100ms;
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/**< BiSS-C max interframe delay */
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volatile uint64_t icssg_clk;
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/**< ICSSG core clock frequency */
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};
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#ifdef __cplusplus
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}
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#endif
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#endif
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