341 lines
17 KiB
C
341 lines
17 KiB
C
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/*
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* Copyright (c) 2023, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ICSS_SDDF_H_
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#define _ICSS_SDDF_H_
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/* Number of SDDF channels per PRU */
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#define ICSSG_NUM_SD_CH ( 9 )
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/* Number of SDDF channels supported by PRU FW */
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#define ICSSG_NUM_SD_CH_FW ( 3 )
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/* ICSSG INTC events */
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/* Compile-time Host event for SDDF samples available.
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Ideally Host would provide this to FW via pseudo-register in DMEM. */
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#define PRU_TRIGGER_HOST_SDDF_EVT ( 2+16 ) /* pr0_pru_mst_intr[2]_intr_req */
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#define RTU_TRIGGER_HOST_SDDF_EVT ( 3+16 ) /* pr0_pru_mst_intr[3]_intr_req */
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/*
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Firmware registers
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*/
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/* FW register base addresses */
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#define PRU_ICSSG_SDDF_CTRL_BASE ( 0x0000 )
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#define PRU_ICSSG_SDDF_CFG_BASE ( 0x0002 )
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#define RTU_ICSSG_SDDF_CTRL_BASE ( 0x0080 )
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#define RTU_ICSSG_SDDF_CFG_BASE ( 0x0082 )
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#if defined (SDDF_PRU_CORE)
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/* SDDF Control */
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#define ICSSG_SDDF_CTRL_BASE ( PRU_ICSSG_SDDF_CTRL_BASE )
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/* SDDF Configuration */
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#define ICSSG_SDDF_CFG_BASE ( PRU_ICSSG_SDDF_CFG_BASE )
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#elif defined (SDDF_RTU_CORE)
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/* SDDF Control */
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#define ICSSG_SDDF_CTRL_BASE ( RTU_ICSSG_SDDF_CTRL_BASE )
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/* SDDF Configuration */
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#define ICSSG_SDDF_CFG_BASE ( RTU_ICSSG_SDDF_CFG_BASE )
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#else
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#endif
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/* FW register sizes (in bytes) */
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/* SDDF Control */
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#define FW_REG_SDDF_CTRL_SZ ( 1 )
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#define FW_REG_SDDF_STAT_SZ ( 1 )
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/* SDDF Configuration */
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#define FW_REG_SDDF_CFG_IEP_CFG_SZ ( 1 )
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#define FW_REG_SDDF_CFG_IEP_CFG_SIM_EPWM_PRD_SZ ( 4 )
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#define FW_REG_SDDF_CFG_SD_CH_ID_SZ ( 4 )
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#define FW_REG_SDDF_CFG_SD_CLK_SZ ( 2 )
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#define FW_REG_SDFM_CFG_OSR_SZ ( 1 )
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#define FW_REG_SDFM_CFG_EN_COMP_SZ ( 2 )
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#define FW_REG_SDFM_CFG_OC_HIGH_THR_SZ ( 2 )
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#define FW_REG_SDFM_CFG_OC_LOW_THR_SZ ( 2 )
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#define FW_REG_SDFM_CFG_ZC_ENABLE_SZ ( 2 )
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#define FW_REG_SDFM_CFG_ZC_THR_SZ ( 4 )
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#define FW_REG_SDFM_CFG_ZC_TRIP_STATUS_SZ ( 1 )
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#define FW_REG_SDFM_CFG_ZC_PREV_VAL_SZ ( 4 )
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#define FW_REG_SDDF_CFG_OSR_SZ ( 1 )
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#define FW_REG_SDDF_CFG_TRIG_SAMPLE_TIME_SZ ( 4 )
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#define FW_REG_SDDF_CFG_TRIG_SAMPLE_CNT_SZ ( 2 )
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#define FW_REG_SDDF_CFG_NC_PRD_IEP_CNT_SZ ( 2 )
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#define FW_REG_SDDF_CFG_OC_PRD_IEP_CNT_SZ ( 2 )
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#define FW_REG_SDDF_CFG_IEP_CFG_SIM_EPWM_PRD_SZ ( 4 )
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#define FW_REG_SDDF_CFG_OUT_SAMP_BUF_SZ ( 4 )
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#define FW_REG_SDFM_CFG_GPIO_VALUE_SZ ( 4 )
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#define FW_REG_SDFM_CFG_GPIO_SET_ADDR_SZ ( 4 )
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#define FW_REG_SDFM_CFG_GPIO_CLR_ADDR_SZ ( 4 )
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#define FW_REG_SDFM_CFG_CURR_VAL_SZ ( 4 )
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/* FW register offsets from base (in bytes) */
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/* SDDF Control */
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#define FW_REG_SDDF_CTRL_OFFSET ( 0x00 )
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#define FW_REG_SDDF_STAT_OFFSET ( 0x01 )
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/* SDDF Configuration */
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#define FW_REG_SDDF_CFG_IEP_CFG_OFFSET ( 0x00 )
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#define FW_REG_SDDF_CFG_IEP_CFG_SIM_EPWM_PRD_OFFSET ( 0x06 )
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#define FW_REG_SDDF_CFG_SD_CLK_OFFSET ( 0x0A )
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#define FW_REG_SDDF_CFG_SD_CH_ID_OFFSET ( 0x0E )
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#define FW_REG_SDFM_CFG_SD_EN_COMP_OFFSET ( 0x12 )
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#define FW_REG_SDFM_CFG_SD_ZC_ENABLE_OFFSET ( 0x16 )
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#define FW_REG_SDFM_CFG_ZC_START_SZ ( 0x18 )
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/*SDFM channel offsets*/
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/*ch0 offset*/
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#define FW_REG_SDDF_CFG_CH0_CH_ID_OFFSET ( 0x1A )
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#define FW_REG_SDDF_CFG_CH0_FILTER_TYPE_OFFSET ( 0x1B )
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#define FW_REG_SDDF_CFG_CH0_OSR_OFFSET ( 0x1C )
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#define FW_REG_SDFM_CFG_OC_HIGH_THR_CH0_OFFSET ( 0x1E )
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#define FW_REG_SDFM_CFG_OC_LOW_THR_CH0_OFFSET ( 0x22 )
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#define FW_REG_SDFM_CFG_OC_ZC_THR_CH0_OFFSET ( 0x26 )
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#define FW_REG_SDFM_CFG_ZC_TRIP_STATUS_CH0_OFFSET ( 0x2A )
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#define SDFM_CFG_ZC_CH0_PREV_VAL_OFFSET ( 0x2E )
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#define FW_REG_SDDF_CFG_CH0_CLOCK_SOURCE_OFFSET ( 0x32 )
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#define FW_REG_SDDF_CFG_CH0_CLOCK_INVERSION_OFFSET ( 0x36 )
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#define SDFM_CFG_HIGH_THR_CH0_WRITE_VAL_OFFSET ( 0x3A )
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#define SDFM_CFG_HIGH_THR_CH0_SET_VAL_ADDR_OFFSET ( 0x3E )
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#define SDFM_CFG_HIGH_THR_CH0_CLR_VAL_ADDR_OFFSET ( 0x42 )
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#define SDFM_CFG_LOW_THR_CH0_WRITE_VAL_OFFSET ( 0x46 )
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#define SDFM_CFG_LOW_THR_CH0_SET_VAL_ADDR_OFFSET ( 0x4A )
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#define SDFM_CFG_LOW_THR_CH0_CLR_VAL_ADDR_OFFSET ( 0x4E )
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#define SDFM_CFG_ZC_THR_CH0_WRITE_VAL_OFFSET ( 0x52 )
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#define SDFM_CFG_ZC_THR_CH0_SET_VAL_ADDR_OFFSET ( 0x56 )
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#define SDFM_CFG_ZC_THR_CH0_CLR_VAL_ADDR_OFFSET ( 0x5A )
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/*ch1 offsets*/
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#define FW_REG_SDDF_CFG_CH1_CH_ID_OFFSET ( 0x5E )
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#define FW_REG_SDDF_CFG_CH1_FILTER_TYPE_OFFSET ( 0x5F )
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#define FW_REG_SDDF_CFG_CH1_OSR_OFFSET ( 0x60 )
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#define FW_REG_SDFM_CFG_OC_HIGH_THR_CH1_OFFSET ( 0x62 )
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#define FW_REG_SDFM_CFG_OC_LOW_THR_CH1_OFFSET ( 0x66 )
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#define FW_REG_SDFM_CFG_OC_ZC_THR_CH1_OFFSET ( 0x6A )
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#define FW_REG_SDFM_CFG_ZC_TRIP_STATUS_CH1_OFFSET ( 0x6E )
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#define SDFM_CFG_ZC_CH1_PREV_VAL_OFFSET ( 0x72 )
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#define FW_REG_SDDF_CFG_CH1_CLOCK_SOURCE_OFFSET ( 0x76 )
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#define FW_REG_SDDF_CFG_CH1_CLOCK_INVERSION_OFFSET ( 0x7A )
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#define SDFM_CFG_HIGH_THR_CH1_WRITE_VAL_OFFSET ( 0x7E )
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#define SDFM_CFG_HIGH_THR_CH1_SET_VAL_ADDR_OFFSET ( 0x82 )
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#define SDFM_CFG_HIGH_THR_CH1_CLR_VAL_ADDR_OFFSET ( 0x86 )
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#define SDFM_CFG_LOW_THR_CH1_WRITE_VAL_OFFSET ( 0x8A )
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#define SDFM_CFG_LOW_THR_CH1_SET_VAL_ADDR_OFFSET ( 0x8E )
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#define SDFM_CFG_LOW_THR_CH1_CLR_VAL_ADDR_OFFSET ( 0x92 )
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#define SDFM_CFG_ZC_THR_CH1_WRITE_VAL_OFFSET ( 0x96 )
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#define SDFM_CFG_ZC_THR_CH1_SET_VAL_ADDR_OFFSET ( 0x9A )
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#define SDFM_CFG_ZC_THR_CH1_CLR_VAL_ADDR_OFFSET ( 0x9E )
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/*ch2 offsets*/
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#define FW_REG_SDDF_CFG_CH2_CH_ID_OFFSET ( 0xA2 )
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#define FW_REG_SDDF_CFG_CH2_FILTER_TYPE_OFFSET ( 0xA3 )
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#define FW_REG_SDDF_CFG_CH2_OSR_OFFSET ( 0xA4 )
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#define FW_REG_SDFM_CFG_OC_HIGH_THR_CH2_OFFSET ( 0xA6 )
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#define FW_REG_SDFM_CFG_OC_LOW_THR_CH2_OFFSET ( 0xAA )
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#define FW_REG_SDFM_CFG_OC_ZC_THR_CH2_OFFSET ( 0xAE )
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#define FW_REG_SDFM_CFG_ZC_TRIP_STATUS_CH2_OFFSET ( 0xB2 )
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#define SDFM_CFG_ZC_CH2_PREV_VAL_OFFSET ( 0xB6 )
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#define FW_REG_SDDF_CFG_CH2_CLOCK_SOURCE_OFFSET ( 0xBA )
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#define FW_REG_SDDF_CFG_CH2_CLOCK_INVERSION_OFFSET ( 0xBE )
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#define SDFM_CFG_HIGH_THR_CH2_WRITE_VAL_OFFSET ( 0xC2 )
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#define SDFM_CFG_HIGH_THR_CH2_SET_VAL_ADDR_OFFSET ( 0xC6 )
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#define SDFM_CFG_HIGH_THR_CH2_CLR_VAL_ADDR_OFFSET ( 0xCA )
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#define SDFM_CFG_LOW_THR_CH2_WRITE_VAL_OFFSET ( 0xCE )
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#define SDFM_CFG_LOW_THR_CH2_SET_VAL_ADDR_OFFSET ( 0xD2 )
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#define SDFM_CFG_LOW_THR_CH2_CLR_VAL_ADDR_OFFSET ( 0xD6 )
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#define SDFM_CFG_ZC_THR_CH2_WRITE_VAL_OFFSET ( 0xDA)
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#define SDFM_CFG_ZC_THR_CH2_SET_VAL_ADDR_OFFSET ( 0xDE )
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#define SDFM_CFG_ZC_THR_CH2_CLR_VAL_ADDR_OFFSET ( 0xE2 )
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/*sample timing offset*/
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#define FW_REG_SDDF_CFG_TRIG_SAMPLE_TIME_OFFSET ( 0xE6 )
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#define FW_REG_SDDF_CFG_OC_PRD_IEP_CNT_OFFSET ( 0xEA )
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#define FW_REG_SDDF_CFG_NC_PRD_IEP_CNT_OFFSET ( 0xEC )
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#define FW_REG_SDDF_CFG_SAMPLE_COUNT ( 0xEE )
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/*Sample output offset*/
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#define FW_REG_SDDF_CFG_OUT_SAMP_BUF_OFFSET ( 0xF2 )
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/*Debug Offset */
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#define DUBG_OFFSET (0x110)
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/* FW register addresses */
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/* Sigma Delta Filter Control */
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#define FW_REG_SDDF_CTRL ( ICSSG_SDDF_CTRL_BASE + FW_REG_SDDF_CTRL_OFFSET )
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/* Sigma Delta Filter Status */
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#define FW_REG_SDDF_STAT ( ICSSG_SDDF_CTRL_BASE + FW_REG_SDDF_STAT_OFFSET )
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/* Sigma Delta Filter Configuration, IEP configuration */
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#define FW_REG_SDDF_CFG_IEP_CFG ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_IEP_CFG_OFFSET )
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/* Sigma Delta Filter Configuration, IEP CMP0 count for simulated EPWM period */
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#define FW_REG_SDDF_CFG_IEP_CFG_SIM_EPWM_PRD ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_IEP_CFG_SIM_EPWM_PRD_OFFSET )
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/* Sigma Delta Filter Configuration, SD channel IDs */
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#define FW_REG_SDDF_CFG_SD_CH_ID ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_SD_CH_ID_OFFSET )
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/* Sigma Delta Filter Configuration, SD clock */
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#define FW_REG_SDDF_CFG_SD_CLK ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_SD_CLK_OFFSET )
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/* Sigma Delta Filter Configuration, OSR */
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#define FW_REG_SDDF_CFG_OSR ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_OSR_OFFSET )
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/* Sigma Delta Filter Configuration, positive threshold for OC detect */
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#define FW_REG_SDDF_CFG_OC_POS_THR ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_OC_POS_THR_OFFSET )
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/* Sigma Delta Filter Configuration, negative threshold for OC detect */
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#define FW_REG_SDDF_CFG_OC_NEG_THR ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_OC_NEG_THR_OFFSET )
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/* Sigma Delta Filter Configuration, Trigger Sample Time */
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#define FW_REG_SDDF_CFG_TRIG_SAMPLE_TIME ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_TRIG_SAMPLE_TIME_OFFSET )
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/* Sigma Delta Filter Configuration, Trigger Sample Count */
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#define FW_REG_SDDF_CFG_OC_PRD_IEP_CNT ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_OC_PRD_IEP_CNT_OFFSET )
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/* Sigma Delta Filter Configuration, NC sampling period IEP counts */
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#define FW_REG_SDDF_CFG_NC_PRD_IEP_CNT ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_NC_PRD_IEP_CNT_OFFSET )
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/* Sigma Delta Filter Configuration, Host Sample Output Buffer */
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#define FW_REG_SDDF_CFG_OUT_SAMP_BUF ( ICSSG_SDDF_CFG_BASE + FW_REG_SDDF_CFG_OUT_SAMP_BUF_OFFSET )
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/*
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Firmware register bit fields
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*/
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/* SDDF_CTRL */
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#define BF_SDDF_EN_MASK ( 0x1 )
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#define BF_PRU_ID_MASK ( 0x3 )
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#define SDDF_CTRL_BF_SDDF_EN_SHIFT ( 0 )
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#define SDDF_CTRL_BF_SDDF_EN_MASK ( BF_SDDF_EN_MASK << SDDF_CTRL_BF_SDDF_EN_SHIFT )
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#define SDDF_CTRL_BF_PRU_ID_SHIFT ( 1 )
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#define SDDF_CTRL_BF_PRU_ID_MASK ( BF_PRU_ID_MASK << SDDF_CTRL_BF_PRU_ID_SHIFT )
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/* SDDF_EN bit field */
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#define BF_SDDF_EN_DISABLE ( 0 )
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#define BF_SDDF_EN_ENABLE ( 1 )
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/* PRU ID bit field */
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#define BF_PRU_ID_0 ( 0 )
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#define BR_PRU_ID_1 ( 1 )
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#define BF_PRU_ID_UNINIT ( 2 )
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/* SDDF_STAT */
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#define BF_SDDF_EN_ACK_MASK ( 0x1 )
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#define BF_PRU_ID_ACK_MASK ( 0x3 )
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#define SDDF_STAT_BF_SDDF_EN_ACK_SHIFT ( 0 )
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#define SDDF_STAT_BF_SDDF_EN_ACK_MASK ( BF_SDDF_EN_ACK_MASK << SDDF_STAT_BF_SDDF_EN_ACK_SHIFT )
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#define SDDF_STAT_BF_PRU_ID_ACK_SHIFT ( 1 )
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#define SDDF_STAT_BF_PRU_ID_ACK_MASK ( BF_PRU_ID_ACK_MASK << SDDF_STAT_BF_PRU_ID_ACK_SHIFT )
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/* IEP_CFG */
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#define BF_IEP_DEFAULT_INC_MASK ( 0xF )
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#define IEP_CFG_BF_IEP_DEFAULT_INC_SHIFT ( 0 )
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#define IEP_CFG_BF_IEP_DEFAULT_INC_MASK ( BF_IEP_DEFAULT_INC_MASK << IEP_CFG_BF_IEP_DEFAULT_INC_SHIFT )
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/* IEP_CFG_EPWM_PRD */
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#define BF_CMP0_CNT_EPWM_PRD_MASK ( 0xFFFFFFFF )
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#define IEP_CFG_BF_CMP0_CNT_EPWM_PRD_SHIFT ( 0 )
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#define IEP_CFG_BF_CMP0_CNT_EPWM_PRD_MASK ( BF_CMP0_CNT_EPWM_PRD_MASK << IEP_CFG_BF_CMP0_CNT_EPWM_PRD_SHIFT )
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/* SDDF_CFG_SD_CH_ID */
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#define BF_SD_CH0_ID_MASK ( 0xF )
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#define BF_SD_CH1_ID_MASK ( 0xF )
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#define BF_SD_CH2_ID_MASK ( 0xF )
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#define SDDF_CFG_BF_SD_CH0_ID_SHIFT ( 0 )
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#define SDDF_CFG_BF_SD_CH1_ID_SHIFT ( 4 )
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#define SDDF_CFG_BF_SD_CH2_ID_SHIFT ( 8 )
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#define SDDF_CFG_BF_SD_CH0_ID_MASK ( BF_SD_CH0_ID_MASK << SDDF_CFG_BF_SD_CH0_ID_SHIFT )
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#define SDDF_CFG_BF_SD_CH1_ID_MASK ( BF_SD_CH1_ID_MASK << SDDF_CFG_BF_SD_CH1_ID_SHIFT )
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#define SDDF_CFG_BF_SD_CH2_ID_MASK ( BF_SD_CH2_ID_MASK << SDDF_CFG_BF_SD_CH2_ID_SHIFT )
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/* SDDF_CFG_SD_CLK */
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#define BF_SD_PRD_CLOCKS_MASK ( 0xFF )
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#define BF_SD_CLK_INV_MASK ( 0x1 )
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#define SDDF_CFG_SD_CLK_BF_SD_PRD_CLOCKS_SHIFT ( 0 )
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#define SDDF_CFG_SD_CLK_BF_SD_PRD_CLOCKS_MASK ( BF_SD_PRD_CLOCKS_MASK << SDDF_CFG_SD_CLK_BF_SD_PRD_CLOCKS_SHIFT )
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#define SDDF_CFG_SD_CLK_BF_SD_CLK_INV_SHIFT ( 8 )
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#define SDDF_CFG_SD_CLK_BF_SD_CLK_INV_MASK ( BF_SD_CLK_INV_MASK << SDDF_CFG_SD_CLK_BF_SD_CLK_INV_SHIFT )
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/* SDDF_CFG_OSR */
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#define BF_OC_OSR_MASK ( 0xFF )
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#define SDDF_CFG_OC_OSR_BF_OSR_SHIFT ( 0 )
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#define SDDF_CFG_OC_OSR_BF_OSR_MASK ( BF_OC_OSR_MASK << SDDF_CFG_OC_OSR_BF_OSR_SHIFT )
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/* SDDF_CFG_OC_POS_THR */
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#define BF_OC_POS_THR_MASK ( 0xFF )
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#define SDDF_CFG_OC_POS_THR_SHIFT ( 0 )
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#define SDDF_CFG_OC_POS_THR_MASK ( BF_OC_POS_THR_MASK << SDDF_CFG_OC_POS_THR_SHIFT )
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/* SDDF_CFG_OC_NEG_THR */
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#define BF_OC_NEG_THR_MASK ( 0xFF )
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#define SDDF_CFG_OC_NEG_THR_SHIFT ( 0 )
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#define SDDF_CFG_OC_NEG_THR_MASK ( BF_OC_NEG_THR_MASK << SDDF_CFG_OC_NEG_THR_SHIFT )
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/* SDFM_CFG_SD_EN_COMP */
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#define SDFM_CFG_BF_SD_CH0_EN_COMP_BIT ( 0x00 )
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#define SDFM_CFG_BF_SD_CH1_EN_COMP_BIT ( 0x01 )
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#define SDFM_CFG_BF_SD_CH2_EN_COMP_BIT ( 0x02 )
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/* SDFM_CFG_ZC_ENABLE */
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#define SDFM_CFG_BF_SD_CH0_ZC_ENABLE_BIT ( 0x00 )
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#define SDFM_CFG_BF_SD_CH1_ZC_ENABLE_BIT ( 0x01 )
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#define SDFM_CFG_BF_SD_CH2_ZC_ENABLE_BIT ( 0x02 )
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/* SDFM_CFG_ZC_START */
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#define SDFM_CFG_BF_SD_CH0_ZC_START_BIT ( 0x00 )
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#define SDFM_CFG_BF_SD_CH1_ZC_START_BIT ( 0x01 )
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#define SDFM_CFG_BF_SD_CH2_ZC_START_BIT ( 0x02 )
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/* SDFM_CFG_TRIP_STATUS */
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#define SDFM_CFG_BF_SD_TRIP_STATUS_HIGH ( 0x01 )
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#define SDFM_CFG_BF_SD_TRIP_STATUS_LOW ( 0x00 )
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/* SDDF_CFG_TRIG_SAMP_TIME */
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#define BF_TRIG_SAMP_TIME_MASK ( 0xFFFF )
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#define SDDF_CFG_TRIG_SAMP_TIME_BF_TRIG_SAMP_TIME_SHIFT \
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( 0 )
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#define SDDF_CFG_TRIG_SAMP_TIME_BF_TRIG_SAMP_TIME_MASK \
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( BF_TRIG_SAMP_TIME_MASK << SDDF_CFG_TRIG_SAMP_TIME_BF_TRIG_SAMP_TIME_SHIFT )
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/* SDDF_CFG_TRIG_SAMPLE_CNT */
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#define BF_TRIG_SAMP_CNT_MASK ( 0xFFFF )
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#define SDDF_CFG_TRIG_SAMP_CNT_BF_TRIG_SAMP_CNT_SHIFT \
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( 0 )
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#define SDDF_CFG_TRIG_SAMP_CNT_BF_TRIG_SAMP_CNT_MASK \
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( BF_TRIG_SAMP_CNT_MASK << SDDF_CFG_TRIG_SAMP_CNT_BF_TRIG_SAMP_CNT_SHIFT )
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/* SDDF_CFG_NC_PRD_IEP_CNT */
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#define BF_NC_PRD_IEP_CNT_MASK ( 0xFF )
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#define SDDF_CFG_NC_PRD_IEP_CNT_SHIFT ( 0 )
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#define SDDF_CFG_NC_PRD_IEP_CNT_MASK ( BF_NC_PRD_IEP_CNT_MASK << SDDF_CFG_NC_PRD_IEP_CNT_SHIFT )
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/* SDDF_CFG_NC_OUT_SAMP_BUF */
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#define BF_NC_OUT_SAMP_BUF_MASK ( 0xFFFF )
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#define SDDF_CFG_NC_OUT_SAMP_BUF_BF_NC_OUT_SAMP_BUF_SHIFT \
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( 0 )
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#define SDDF_CFG_NC_OUT_SAMP_BUF_BF_NC_OUT_SAMP_BUF_MASK \
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( BF_NC_OUT_SAMP_BUF_MASK << SDDF_CFG_NC_OUT_SAMP_BUF_BF_NC_OUT_SAMP_BUF_SHIFT )
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#endif
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