336 lines
12 KiB
C
336 lines
12 KiB
C
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/*
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* Copyright (C) 2023 Texas Instruments Incorporated
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include<stdio.h>
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#include<stdint.h>
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#include<math.h>
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#include <drivers/pruicss.h>
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#include <drivers/hw_include/hw_types.h>
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#include <drivers/hw_include/tistdtypes.h>
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#include <kernel/dpl/ClockP.h>
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#include "endat_periodic_trigger.h"
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#include <drivers/soc.h>
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#include <position_sense/endat/include/endat_drv.h>
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#include <position_sense/endat/include/endat_interface.h>
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HwiP_Params hwiPrms;
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static HwiP_Object gIcssgEncoderHwiObject0; /* ICSSG EnDat PRU FW HWI */
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static HwiP_Object gIcssgEncoderHwiObject1; /* ICSSG EnDat PRU FW HWI */
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static HwiP_Object gIcssgEncoderHwiObject2; /* ICSSG EnDat PRU FW HWI */
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/* ICSSG Interrupt settings */
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#define ICSSG_PRU_ENDAT_INT_NUM ( CSLR_R5FSS0_CORE0_INTR_PRU_ICSSG0_PR1_HOST_INTR_PEND_0 )
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uint32_t gPruEnDatIrqCnt0;
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uint32_t gPruEnDatIrqCnt1;
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uint32_t gPruEnDatIrqCnt2;
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/*global variable */
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void *gPruss_iep;
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PRUICSS_Handle gPruIcssXHandle;
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/* ICSS INTC configuration */
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static const PRUICSS_IntcInitData gPruicssIntcInitdata = PRUICSS_INTC_INITDATA;
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void endat_config_iep(struct endat_periodic_interface *endat_periodic_interface)
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{
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/*reset iep timer*/
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void *pruss_iep = endat_periodic_interface->pruss_iep;
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struct endat_pruss_xchg *pruss_xchg = endat_periodic_interface->pruss_dmem;
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uint8_t temp;
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uint8_t event;
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uint32_t cmp_reg0;
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uint32_t cmp_reg1;
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uint32_t event_clear;
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uint64_t cmp0 = 0;
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/*clear IEP*/
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temp = HW_RD_REG8((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_GLOBAL_CFG_REG );
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temp &= 0xFE;
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HW_WR_REG8((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_GLOBAL_CFG_REG, temp);
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/* cmp cfg reg */
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event = HW_RD_REG8((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_CMP_CFG_REG);
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event_clear = HW_RD_REG8((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_CMP_STATUS_REG);
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/*enable IEP reset by cmp0 event*/
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event |= IEP_CMP0_ENABLE;
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event |= IEP_RST_CNT_EN;
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event_clear |= 1;
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/*set IEP counter to ZERO*/
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HW_WR_REG32((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_COUNT_REG0, 0);
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HW_WR_REG32((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_COUNT_REG1, 0);
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/*Clear all event & configure*/
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if(endat_periodic_interface->load_share)
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{
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event |= pruss_xchg->config[0].channel==1?(0x1 << 4 ):0; //CMP3 for ch0
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event |= pruss_xchg->config[1].channel==2?(0x1 << 6 ):0; //CMP5 for Ch1
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event |= pruss_xchg->config[2].channel==4?(0x1 << 7 ):0; //CMP6 for CH2
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/*clear event*/
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event_clear |= pruss_xchg->config[0].channel==1?(0x1 << 3 ):0; //CMP3 for ch0
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event_clear |= pruss_xchg->config[1].channel==2?(0x1 << 5 ):0; //CMP5 for Ch1
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event_clear |= pruss_xchg->config[2].channel==4?(0x1 << 6 ):0; //CMP6 for CH2
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if(pruss_xchg->config[0].channel)
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{
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cmp_reg0 = (endat_periodic_interface->cmp3 & 0xffffffff) - IEP_DEFAULT_INC;
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cmp_reg1 = (endat_periodic_interface->cmp3>>32 & 0xffffffff);
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HW_WR_REG32((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_CMP3_REG0, cmp_reg0);
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HW_WR_REG32((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_CMP3_REG1, cmp_reg1);
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cmp0 = cmp0 > endat_periodic_interface->cmp3 ? cmp0: endat_periodic_interface->cmp3;
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}
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if(pruss_xchg->config[1].channel)
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{
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cmp_reg0 = (endat_periodic_interface->cmp5 & 0xffffffff) - IEP_DEFAULT_INC;
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cmp_reg1 = (endat_periodic_interface->cmp5>>32 & 0xffffffff);
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HW_WR_REG32((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_CMP5_REG0, cmp_reg0);
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HW_WR_REG32((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_CMP5_REG1, cmp_reg1);
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cmp0 = cmp0 > endat_periodic_interface->cmp5 ? cmp0: endat_periodic_interface->cmp5;
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}
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if(pruss_xchg->config[2].channel)
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{
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cmp_reg0 = (endat_periodic_interface->cmp6 & 0xffffffff) - IEP_DEFAULT_INC;
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cmp_reg1 = (endat_periodic_interface->cmp6>>32 & 0xffffffff);
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HW_WR_REG32((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_CMP6_REG0, cmp_reg0);
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HW_WR_REG32((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_CMP6_REG1, cmp_reg1);
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cmp0 = cmp0 > endat_periodic_interface->cmp6 ? cmp0: endat_periodic_interface->cmp6;
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}
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}
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else
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{
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event |= (0x1 << 4 );
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event_clear |= (0x1 << 3);
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cmp_reg0 = (endat_periodic_interface->cmp3 & 0xffffffff) - IEP_DEFAULT_INC;
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cmp_reg1 = (endat_periodic_interface->cmp3>>32 & 0xffffffff);
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HW_WR_REG32((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_CMP3_REG0, cmp_reg0);
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HW_WR_REG32((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_CMP3_REG1, cmp_reg1);
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cmp0 = endat_periodic_interface->cmp3;
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}
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/*clear event*/
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HW_WR_REG8((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_CMP_STATUS_REG, event_clear);
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/*enable event*/
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HW_WR_REG8((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_CMP_CFG_REG, event);
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/*configure cmp0 registers*/
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cmp0 = 2*cmp0;
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cmp_reg0 = (cmp0 & 0xffffffff) - IEP_DEFAULT_INC;
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cmp_reg1 = (cmp0>>32 & 0xffffffff);
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HW_WR_REG32((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_CMP0_REG0, cmp_reg0);
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HW_WR_REG32((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_CMP0_REG1, cmp_reg1);
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/*write IEP default increment & IEP start*/
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temp = HW_RD_REG8((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_GLOBAL_CFG_REG );
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temp &= 0x0F;
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temp |= 0x10;
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temp |= IEP_COUNTER_EN;
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HW_WR_REG8((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_GLOBAL_CFG_REG, temp);
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}
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void endat_interrupt_config(struct endat_periodic_interface *endat_periodic_interface)
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{
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struct endat_pruss_xchg *pruss_xchg = endat_periodic_interface->pruss_dmem;
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int32_t status;
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if(endat_periodic_interface->load_share)
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{
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if(pruss_xchg->config[0].channel)
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{
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/* Register & enable ICSSG EnDat PRU FW interrupt */
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HwiP_Params_init(&hwiPrms);
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hwiPrms.intNum = ICSSG_PRU_ENDAT_INT_NUM;
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hwiPrms.callback = &pruEnDatIrqHandler0;
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hwiPrms.args = 0;
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hwiPrms.isPulse = FALSE;
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hwiPrms.isFIQ = FALSE;
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status = HwiP_construct(&gIcssgEncoderHwiObject0, &hwiPrms);
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DebugP_assert(status == SystemP_SUCCESS);
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}
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if(pruss_xchg->config[1].channel)
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{
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/* Register & enable ICSSG EnDat PRU FW interrupt */
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HwiP_Params_init(&hwiPrms);
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hwiPrms.intNum = ICSSG_PRU_ENDAT_INT_NUM + 1;
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hwiPrms.callback = &pruEnDatIrqHandler1;
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hwiPrms.args = 0;
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hwiPrms.isPulse = FALSE;
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hwiPrms.isFIQ = FALSE;
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status = HwiP_construct(&gIcssgEncoderHwiObject1, &hwiPrms);
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DebugP_assert(status == SystemP_SUCCESS);
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}
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if(pruss_xchg->config[2].channel)
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{
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/* Register & enable ICSSG EnDat PRU FW interrupt */
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HwiP_Params_init(&hwiPrms);
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hwiPrms.intNum = ICSSG_PRU_ENDAT_INT_NUM + 2;
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hwiPrms.callback = &pruEnDatIrqHandler2;
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hwiPrms.args = 0;
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hwiPrms.isPulse = FALSE;
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hwiPrms.isFIQ = FALSE;
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status = HwiP_construct(&gIcssgEncoderHwiObject2, &hwiPrms);
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DebugP_assert(status == SystemP_SUCCESS);
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}
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}
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else
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{
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/* Register & enable ICSSG EnDat PRU FW interrupt */
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HwiP_Params_init(&hwiPrms);
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hwiPrms.intNum = ICSSG_PRU_ENDAT_INT_NUM;
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hwiPrms.callback = &pruEnDatIrqHandler0;
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hwiPrms.args = 0;
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hwiPrms.isPulse = FALSE;
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hwiPrms.isFIQ = FALSE;
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status = HwiP_construct(&gIcssgEncoderHwiObject0, &hwiPrms);
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DebugP_assert(status == SystemP_SUCCESS);
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}
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}
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uint32_t endat_config_periodic_mode(struct endat_periodic_interface *endat_periodic_interface, PRUICSS_Handle handle)
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{
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int32_t status;
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gPruIcssXHandle = handle;
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gPruss_iep = endat_periodic_interface->pruss_iep;
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/*configure IEP*/
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endat_config_iep(endat_periodic_interface);
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/* Initialize ICSS INTC */
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status = PRUICSS_intcInit(gPruIcssXHandle, &gPruicssIntcInitdata);
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if (status != SystemP_SUCCESS)
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{
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return 0;
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}
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/*config Interrupt*/
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endat_interrupt_config(endat_periodic_interface);
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return 1;
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}
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void endat_stop_periodic_continuous_mode(struct endat_periodic_interface *endat_periodic_interface)
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{
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/*reset iep timer*/
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void *pruss_iep = endat_periodic_interface->pruss_iep;
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uint8_t temp;
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/*clear IEP*/
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temp = HW_RD_REG8((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_GLOBAL_CFG_REG );
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temp &= 0xFE;
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HW_WR_REG8((uint8_t*)pruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_GLOBAL_CFG_REG, temp);
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}
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/* PRU EnDat FW IRQ handler */
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void pruEnDatIrqHandler0(void *args)
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{
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/* debug, inncrement PRU SDFM IRQ count */
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gPruEnDatIrqCnt0++;
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/* clear Cmp3 event*/
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uint32_t event_clear;
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event_clear = HW_RD_REG8((uint8_t*)gPruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_CMP_STATUS_REG);
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event_clear |= IEP_CMP3_EVNT;
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HW_WR_REG8((uint8_t*)gPruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_CMP_STATUS_REG, event_clear);
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/* Clear interrupt at source */
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/* Write 18 to ICSSG_STATUS_CLR_INDEX_REG
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Firmware: TRIGGER_HOST_SDFM_IRQ defined as 18
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18 = 16+2, 2 is Host Interrupt Number. See AM64x TRM.
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*/
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PRUICSS_clearEvent(gPruIcssXHandle, PRU_TRIGGER_HOST_SDFM_EVT0);
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}
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/* PRU EnDat FW IRQ handler */
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void pruEnDatIrqHandler1(void *args)
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{
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/* debug, inncrement PRU SDFM IRQ count */
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gPruEnDatIrqCnt1++;
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/* clear Cmp5 event*/
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uint32_t event_clear;
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event_clear = HW_RD_REG8((uint8_t*)gPruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_CMP_STATUS_REG);
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event_clear |= IEP_CMP5_EVNT;
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HW_WR_REG8((uint8_t*)gPruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_CMP_STATUS_REG, event_clear);
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/* Clear interrupt at source */
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/* Write 18 to ICSSG_STATUS_CLR_INDEX_REG
|
||
|
|
Firmware: TRIGGER_HOST_SDFM_IRQ defined as 18
|
||
|
|
18 = 16+2, 2 is Host Interrupt Number. See AM64x TRM.
|
||
|
|
*/
|
||
|
|
|
||
|
|
PRUICSS_clearEvent(gPruIcssXHandle, PRU_TRIGGER_HOST_SDFM_EVT1);
|
||
|
|
|
||
|
|
|
||
|
|
}
|
||
|
|
/* PRU EnDat FW IRQ handler */
|
||
|
|
void pruEnDatIrqHandler2(void *args)
|
||
|
|
{
|
||
|
|
/* debug, inncrement PRU SDFM IRQ count */
|
||
|
|
gPruEnDatIrqCnt2++;
|
||
|
|
|
||
|
|
/* clear Cmp6 event*/
|
||
|
|
uint32_t event_clear;
|
||
|
|
event_clear = HW_RD_REG8((uint8_t*)gPruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_CMP_STATUS_REG);
|
||
|
|
event_clear |= IEP_CMP6_EVNT;
|
||
|
|
HW_WR_REG8((uint8_t*)gPruss_iep + CSL_ICSS_G_PR1_IEP1_SLV_CMP_STATUS_REG, event_clear);
|
||
|
|
|
||
|
|
/* Clear interrupt at source */
|
||
|
|
/* Write 18 to ICSSG_STATUS_CLR_INDEX_REG
|
||
|
|
Firmware: TRIGGER_HOST_SDFM_IRQ defined as 18
|
||
|
|
18 = 16+2, 2 is Host Interrupt Number. See AM64x TRM.
|
||
|
|
*/
|
||
|
|
PRUICSS_clearEvent(gPruIcssXHandle, PRU_TRIGGER_HOST_SDFM_EVT2);
|
||
|
|
|
||
|
|
|
||
|
|
}
|