107 lines
3.9 KiB
C
107 lines
3.9 KiB
C
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; sddf_macros.h
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;
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; Copyright (c) 2023, Texas Instruments Incorporated
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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;
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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;
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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;
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; * Neither the name of Texas Instruments Incorporated nor the names of
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; its contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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.if !$defined("__sddf_macros_h")
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__sddf_macros_h .set 1
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.include "sddf.h"
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;
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; Macros
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;
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WRITE_C24_BLK_INDEX .macro blk_index
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; Set DMEM (C24) block offset
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LDI TREG0.b0, blk_index
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SBCO &TREG0.b0, CT_PRU_ICSSG_CTRL, PRUx_CNTLSELF_CONST_IDX0_REG, 1
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NOP ; delay for update to land?
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.endm
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; Set SD HW registers base pointer
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SET_SD_HW_REG_BASE_PTR .macro base_ptr
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; Load TR0.b0 <- FW_REG_SDDF_CTRL
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LBCO &TREG0.b0, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_CTRL, FW_REG_SDDF_CTRL_SZ
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; Check PRU ID 0 or 1
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QBBS pru_id1?, TREG0, SDDF_CTRL_BF_PRU_ID_SHIFT
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pru_id0?:
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LDI32 base_ptr, PRUx_CFG_BASE+ICSSG_CFG_PRU0_SD0_CLK
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QBA set_sd_hw_reg_base_ptr_end?
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pru_id1?:
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LDI32 base_ptr, PRUx_CFG_BASE+ICSSG_CFG_PRU1_SD0_CLK
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set_sd_hw_reg_base_ptr_end?:
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.endm
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; Configure Triggered mode sample count
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;CFG_TRIG_MODE_SAMP_CNT .macro samp_cnt
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; Load samp_cnt <- SDDF_CFG_TRIG_SAMPLE_CNT
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; LBCO &samp_cnt, CT_PRU_ICSSG_LOC_DMEM, FW_REG_SDDF_CFG_TRIG_SAMPLE_CNT, FW_REG_SDDF_CFG_TRIG_SAMPLE_CNT_SZ
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; .endm
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; Wait until shadow flag of the channel is set & clear the flag
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; args - ch_idx : SD channel index {0...ICSSG_NUM_SD_CH-1}
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;; updates - TREG0.w2 : channel sample buffer offset
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;
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M_WAIT_SHADOW_FLAG_AND_CLR .macro ch_idx
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; Place ch_idx in R30[29-26], channel_select
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LSL TREG1.b0, ch_idx, 2
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SET TREG1.b0.t1
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MOV R30.b3, TREG1.b0
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NOP
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wait_for_shadow_update_cont?:
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; R31[24], shadow_update_flag for ICSS
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; R31[28], shadow_update_flag for ICSSG
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QBBC wait_for_shadow_update_cont?, R31, 28
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; R31[24], shadow_update_flag_clr for ICSS/ICSSG
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SET R31, R31.t24
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.endm
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.endif ; __sddf_macros_h
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; Calculates Sinc3 sample value from ACC3 & Sinc3 variables
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; args - DN1, DN3, DN5 : Sinc3 differntiator state variables
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; expects - ACC3 value in DN0, mask in MASK_REG
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; uses - CN3, CN4, CN5
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; result - CN5 : Output sample
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;
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M_ACC3_PROCESS .macro DN1, DN3, DN5
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RSB CN3, DN1, DN0
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MOV DN1, DN0
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RSB CN4, DN3, CN3
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MOV DN3, CN3
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RSB CN5, DN5, CN4
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MOV DN5, CN4
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AND CN5, CN5, MASK_REG ; apply limit
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.endm
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