108 lines
2.8 KiB
Plaintext
108 lines
2.8 KiB
Plaintext
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%%{
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let options = args.options;
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let stackSize = 0x10000;
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let heapSize = 0x20000;
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let isSingleCore = true;
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let useDdr = true;
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let addrBaseDdr = 0x80000000;
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let codeDataSizeDdr = 0x1000000;
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/* if no options given use defaults */
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if(options && options.stackSize)
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stackSize = options.stackSize;
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if(options && options.heapSize)
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heapSize = options.heapSize;
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if(isSingleCore == true) {
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codeDataAddrDdr = addrBaseDdr;
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codeDataSizeDdr = 0x1000000 * 2;
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}
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else {
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if(args.project.cpu == "a53ss0-0")
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{
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codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*0;
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}
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if(args.project.cpu == "a53ss0-1")
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{
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codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*1;
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}
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}
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if(options && options.addrBaseDdr)
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addrBaseDdr = options.addrBaseDdr;
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if(options && options.codeDataSizeDdr)
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codeDataSizeDdr = options.codeDataSizeDdr;
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%%}
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ENTRY(_c_int00)
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__TI_STACK_SIZE = `stackSize`;
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__TI_HEAP_SIZE = `heapSize`;
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MEMORY
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{
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% if(useDdr) {
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DDR : ORIGIN = 0x`(codeDataAddrDdr).toString(16).toUpperCase()`, LENGTH = 0x`(codeDataSizeDdr).toString(16).toUpperCase()`
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% }
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/* shared memory segments */
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/* On A53,
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* - make sure there is a MMU entry which maps below regions as non-cache
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*/
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USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80
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LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80
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RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
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}
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SECTIONS {
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.vecs : {} > DDR
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.text : {} > DDR
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.rodata : {} > DDR
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.data : ALIGN (8) {
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__data_load__ = LOADADDR (.data);
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__data_start__ = .;
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*(.data)
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*(.data*)
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. = ALIGN (8);
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__data_end__ = .;
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} > DDR
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/* General purpose user shared memory, used in some examples */
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.bss.user_shared_mem (NOLOAD) : { KEEP(*(.bss.user_shared_mem)) } > USER_SHM_MEM
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/* this is used when Debug log's to shared memory are enabled, else this is not used */
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.bss.log_shared_mem (NOLOAD) : { KEEP(*(.bss.log_shared_mem)) } > LOG_SHM_MEM
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/* this is used only when IPC RPMessage is enabled, else this is not used */
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.bss.ipc_vring_mem (NOLOAD) : { KEEP(*(.bss.ipc_vring_mem)) } > RTOS_NORTOS_IPC_SHM_MEM
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.bss : {
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__bss_start__ = .;
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*(.bss)
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*(.bss.*)
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. = ALIGN (8);
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*(COMMON)
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__bss_end__ = .;
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. = ALIGN (8);
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} > DDR
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.heap (NOLOAD) : {
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__heap_start__ = .;
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KEEP(*(.heap))
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. = . + __TI_HEAP_SIZE;
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__heap_end__ = .;
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} > DDR
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.stack (NOLOAD) : ALIGN(16) {
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__TI_STACK_BASE = .;
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KEEP(*(.stack))
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. = . + __TI_STACK_SIZE;
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__TI_STACK_BASE1 = .;
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KEEP(*(.stack))
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. = . + __TI_STACK_SIZE;
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} > DDR
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}
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