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	.include "../../../../pru_io/firmware/common/icss_regs.inc"
	.include "../../../../pru_io/firmware/common/icss_cfg_regs.inc"

	.asg	R30.t24,	ENDAT_CH0_RX_EN
	.asg	R31.t27,	ENDAT_CH0_RX_CLR_OVF
	.asg	R31.t24,	ENDAT_CH0_RX_CLR_VALID
	.asg	R31.t27,	ENDAT_CH0_RX_OVF
	.asg	R31.t24,	ENDAT_CH0_RX_VALID

	.asg	R30.t25,	ENDAT_CH1_RX_EN
	.asg	R31.t28,	ENDAT_CH1_RX_CLR_OVF
	.asg	R31.t25,	ENDAT_CH1_RX_CLR_VALID
	.asg	R31.t28,	ENDAT_CH1_RX_OVF
	.asg	R31.t25,	ENDAT_CH1_RX_VALID

	.asg	R30.t26,	ENDAT_CH2_RX_EN
	.asg	R31.t29,	ENDAT_CH2_RX_CLR_OVF
	.asg	R31.t26,	ENDAT_CH2_RX_CLR_VALID
	.asg	R31.t29,	ENDAT_CH2_RX_OVF
	.asg	R31.t26,	ENDAT_CH2_RX_VALID


; Channel select bits R30[17:16]
ENDAT_TX_CH0_SEL	.set					0
ENDAT_TX_CH1_SEL	.set					1
ENDAT_TX_CH2_SEL	.set					2

; CLK MODE bits R30[20:19]
ENDAT_TX_CLK_MODE_FREERUN_STOPLOW	.set	(0 << 3)
ENDAT_TX_CLK_MODE_FREERUN_STOPHIGH	.set	(1 << 3)
ENDAT_TX_CLK_MODE_FREERUN	.set			(2 << 3)
ENDAT_TX_CLK_MODE_STOPHIGH_AFTER_TX	.set	(3 << 3)

	.asg	R31.t18,	ENDAT_TX_CHANNEL_GO
	.asg	R31.t19,	ENDAT_TX_GLOBAL_REINIT
	.asg	R31.t20,	ENDAT_TX_GLOBAL_GO

	.asg	R31.t5,	ENDAT_CH0_TX_GLOBAL_REINIT_ACTIVE
	.asg	R31.t5,	ENDAT_CH0_TX_BUSY
	.asg	R31.t0,	ENDAT_CH0_TX_OVERUN
	.asg	R31.t1,	ENDAT_CH0_TX_UNDERRUN

	.asg	R31.t13,	ENDAT_CH1_TX_GLOBAL_REINIT_ACTIVE
	.asg	R31.t13,	ENDAT_CH1_TX_BUSY
	.asg	R31.t8,	ENDAT_CH1_TX_OVERUN
	.asg	R31.t9,	ENDAT_CH1_TX_UNDERRUN

	.asg	R31.t21,	ENDAT_CH2_TX_GLOBAL_REINIT_ACTIVE
	.asg	R31.t21,	ENDAT_CH2_TX_BUSY
	.asg	R31.t16,	ENDAT_CH2_TX_OVERUN
	.asg	R31.t17,	ENDAT_CH2_TX_UNDERRUN


; ENDAT
