122 lines
6.3 KiB
C
122 lines
6.3 KiB
C
//###########################################################################
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//
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// FILE: hw_ints.h
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//
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// TITLE: Macros that define the interrupt assignment.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_INTS_H
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#define HW_INTS_H
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//*****************************************************************************
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// The following are defines for the fault assignments.
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//*****************************************************************************
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#define FAULT_NMI 2U // NMI
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#define FAULT_HARD 3U // HardFault
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#define FAULT_MPU 4U // MemManage
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#define FAULT_BUS 5U // BusFault
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#define FAULT_USAGE 6U // UsageFault
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#define FAULT_SVCALL 11U // SVCall
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#define FAULT_DEBUG 12U // Debug Monitor
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#define FAULT_PENDSV 14U // PendSV
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#define FAULT_SYSTICK 15U // SysTick
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//*****************************************************************************
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// The following are defines for the interrupt assignments.
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//*****************************************************************************
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#define INT_MCANSS_0 16U // MCANSS_0 Interrupt
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#define INT_MCANSS_1 17U // MCANSS_1 Interrupt
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#define INT_MCANSS_WAKE_AND_TS_PLS 18U // MCANSS_WAKE_AND_TS_PLS Interrupt
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#define INT_MCANSS_ECC_CORR_PLS 19U // MCANSS_ECC_CORR_PLS Interrupt
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#define INT_ECAT 21U // ECAT Interrupt
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#define INT_ECAT_SYNC0 22U // ECAT_SYNC0 Interrupt
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#define INT_ECAT_SYNC1 23U // ECAT_SYNC1 Interrupt
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#define INT_ECAT_RST 24U // ECAT_RST Interrupt
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#define INT_CANA0 25U // CANA0 Interrupt
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#define INT_CANA1 26U // CANA1 Interrupt
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#define INT_CANB0 27U // CANB0 Interrupt
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#define INT_CANB1 28U // CANB1 Interrupt
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#define INT_EMAC 29U // EMAC Interrupt
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#define INT_EMAC_TX0 30U // EMAC_TX0 Interrupt
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#define INT_EMAC_TX1 31U // EMAC_TX1 Interrupt
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#define INT_EMAC_RX0 32U // EMAC_RX0 Interrupt
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#define INT_EMAC_RX1 33U // EMAC_RX1 Interrupt
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#define INT_UART0 34U // UART0 Interrupt
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#define INT_SSI0 36U // SSI0 Interrupt
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#define INT_I2C0 38U // I2C0 Interrupt
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#define INT_USB0 40U // USB Interrupt
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#define INT_UDMA_SW 41U // UDMA_SW Interrupt
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#define INT_UDMA_ERR 42U // UDMA_ERR Interrupt
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#define INT_CPU1TOCMIPC0 45U // CPU1TOCMIPC0 Interrupt
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#define INT_CPU1TOCMIPC1 46U // CPU1TOCMIPC1 Interrupt
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#define INT_CPU1TOCMIPC2 47U // CPU1TOCMIPC2 Interrupt
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#define INT_CPU1TOCMIPC3 48U // CPU1TOCMIPC3 Interrupt
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#define INT_CPU1TOCMIPC4 49U // CPU1TOCMIPC4 Interrupt
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#define INT_CPU1TOCMIPC5 50U // CPU1TOCMIPC5 Interrupt
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#define INT_CPU1TOCMIPC6 51U // CPU1TOCMIPC6 Interrupt
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#define INT_CPU1TOCMIPC7 52U // CPU1TOCMIPC7 Interrupt
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#define INT_CPU2TOCMIPC0 53U // CPU2TOCMIPC0 Interrupt
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#define INT_CPU2TOCMIPC1 54U // CPU2TOCMIPC1 Interrupt
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#define INT_CPU2TOCMIPC2 55U // CPU2TOCMIPC2 Interrupt
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#define INT_CPU2TOCMIPC3 56U // CPU2TOCMIPC3 Interrupt
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#define INT_CPU2TOCMIPC4 57U // CPU2TOCMIPC4 Interrupt
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#define INT_CPU2TOCMIPC5 58U // CPU2TOCMIPC5 Interrupt
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#define INT_CPU2TOCMIPC6 59U // CPU2TOCMIPC6 Interrupt
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#define INT_CPU2TOCMIPC7 60U // CPU2TOCMIPC7 Interrupt
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#define INT_FMC 61U // FMC Interrupt
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#define INT_FMC_CORR_ERR 62U // FMC_CORR_ERR Interrupt
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#define INT_AES 63U // AES Interrupt
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#define INT_TIMER0 64U // TIMER0 Interrupt
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#define INT_TIMER1 65U // TIMER1 Interrupt
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#define INT_TIMER2 66U // TIMER2 Interrupt
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#define INT_CMRAM_TESTERROR_LOG 67U // CMRAM_TESTERROR_LOG Interrupt
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//*****************************************************************************
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// The following are defines for the total number of interrupts.
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//*****************************************************************************
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#define NUM_INTERRUPTS 80U
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//*****************************************************************************
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// The following are defines for the total number of priority levels.
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//*****************************************************************************
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#define NUM_PRIORITY 8U
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#define NUM_PRIORITY_BITS 3U
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#endif // HW_INTS_H
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