471 lines
18 KiB
JavaScript
471 lines
18 KiB
JavaScript
let Common = system.getScript("/driverlib/Common.js");
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let Pinmux = system.getScript("/driverlib/pinmux.js");
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let AccProt = system.getScript("/driverlib/mecfgAccProt.js");
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let device_driverlib_peripheral =
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system.getScript("/driverlib/device_driverlib_peripherals/" +
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Common.getDeviceName().toLowerCase() + "_memcfg.js");
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let device_driverlib_memmap =
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system.getScript("/driverlib/device_driverlib_peripherals/" +
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Common.getDeviceName().toLowerCase() + "_memmap.js");
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/* Intro splash on GUI */
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let longDescription = ``;
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longDescription += "* [Device TRM](" + Common.getDeviceTRM() + ") \n - For GSRAM blocks configured to be owned by CPU2: the code for Initialization, Access Protection, and Lock Configs will be generated on CPU2";
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/* Array of MEMCFG configurables that are common across device families */
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let staticConfig = []
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let LSRAMOwnerConfig = []
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let GSRAMOwnerConfig = []
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let AccessConfig = []
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let InitRAM = []
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let LockConfig = []
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let ViolIntConfig = []
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let CorrErrIntConfig = []
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let ROMConfig = []
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/* Section : LSRAM Configuration */
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if(device_driverlib_peripheral.MemCfg_LSRAMControllerSel)
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{
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device_driverlib_peripheral.MEMCFG_SECT.
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forEach((element, index) =>
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{
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if ((element.name.includes("MEMCFG_SECT_LS")) && (element.name != "MEMCFG_SECT_LSX_ALL"))
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{
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LSRAMOwnerConfig.push(
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{
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name: "config_" + element.name,
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displayName : element.displayName,
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options : [
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{name: "CPU_memory", displayName: "CPU dedicated memory"},
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{name: "CLA_data", displayName: "CPU/CLA shared data memory"},
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{name: "CLA_prog", displayName: "CLA program memory"},
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],
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default : "CPU_memory"
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}
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)
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}
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}
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);
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}
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/* Section : GSRAM Configuration */
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if (Common.isContextCPU1())
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{
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if(device_driverlib_peripheral.MemCfg_GSRAMControllerSel)
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{
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device_driverlib_peripheral.MEMCFG_SECT.
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forEach((element, index) =>
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{
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if ((element.name.includes("MEMCFG_SECT_GS")) && (element.name != "MEMCFG_SECT_GSX_ALL"))
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{
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GSRAMOwnerConfig.push(
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{
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name : "config_" + element.name,
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displayName: element.displayName,
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options : device_driverlib_peripheral.MemCfg_GSRAMControllerSel,
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default : device_driverlib_peripheral.MemCfg_GSRAMControllerSel[0].name
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}
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)
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}
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}
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);
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}
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}
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/* Section : ROM config */
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if(["F2838x", "F2837xD", "F2837xS", "F2807x"].includes(system.deviceData.deviceId))
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{
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ROMConfig = [
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{
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name : "rom_waitstate",
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displayName: "Enable ROM wait state",
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description: "If enabled, CPU accesses to ROM are 1-wait",
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default : true
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},
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{
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name : "rom_prefetch",
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displayName: "Enable ROM prefetch",
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description: "Enable prefetch for secure ROM and boot ROM",
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default : false
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},
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]
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}
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/* Section : Access Protection */
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AccProt.AcessProtectionRAMs[system.deviceData.deviceId.toLowerCase()].
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forEach((element, index) =>
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{
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var ramMacro = "MEMCFG_SECT_" + element.name
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if (ramMacro[12]!="G") // Global ram has own if statement so description is only on GSRAM
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{
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if(device_driverlib_peripheral.MEMCFG_SECT.map(a=>a.name).includes(ramMacro) && (Common.isContextCPU1() || !ramMacro.includes("TOCM")))
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{
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var AvailableOptions = []
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if(element.access.includes("FETCHPROT"))
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AvailableOptions.push({name : "MEMCFG_PROT_ALLOWCPUFETCH", displayName: "CPU fetch allowed"})
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if(element.access.includes("CPUWRPROT"))
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AvailableOptions.push({name : "MEMCFG_PROT_ALLOWCPUWRITE", displayName: "CPU write allowed"})
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if(element.access.includes("DMAWRPROT"))
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AvailableOptions.push({name : "MEMCFG_PROT_ALLOWDMAWRITE", displayName: "DMA write allowed"})
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if(element.access.includes("HICWRPROT"))
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AvailableOptions.push({name : "MEMCFG_PROT_ALLOWHICWRITE", displayName: "HIC write allowed"})
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if (ramMacro.includes("MSGCPUTOCPU")){
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let ramNumber = ramMacro[23]; // get number from end of ram macro
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AccessConfig.push(
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{
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name : "access_" + ramMacro,
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displayName : "CPU-to-CPU message RAM"+ ramNumber.toString() + " Access",
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minSelections: 0,
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options : AvailableOptions,
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default : AvailableOptions.map(a=>a.name)
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})
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}
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if (ramMacro.includes("MSGCPUTOCM")){ // get number from end of ram macro
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let ramNumber = ramMacro[22];
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AccessConfig.push(
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{
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name : "access_" + ramMacro,
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displayName : "CPU-to-CM message RAM"+ ramNumber.toString() + " Access",
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minSelections: 0,
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options : AvailableOptions,
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default : AvailableOptions.map(a=>a.name)
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})
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}
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if ((!ramMacro.includes("MSGCPUTOCPU")) && (!ramMacro.includes("MSGCPUTOCM"))){
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AccessConfig.push(
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{
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name : "access_" + ramMacro,
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displayName : element.name + " RAM Access",
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minSelections: 0,
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options : AvailableOptions,
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default : AvailableOptions.map(a=>a.name)
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})
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}
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}
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}
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if (ramMacro[12]=="G" && (Common.isContextCPU1()))
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{
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if(device_driverlib_peripheral.MEMCFG_SECT.map(a=>a.name).includes(ramMacro))
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{
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var AvailableOptions = []
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if(element.access.includes("FETCHPROT"))
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AvailableOptions.push({name : "MEMCFG_PROT_ALLOWCPUFETCH", displayName: "CPU fetch allowed"})
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if(element.access.includes("CPUWRPROT"))
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AvailableOptions.push({name : "MEMCFG_PROT_ALLOWCPUWRITE", displayName: "CPU write allowed"})
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if(element.access.includes("DMAWRPROT"))
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AvailableOptions.push({name : "MEMCFG_PROT_ALLOWDMAWRITE", displayName: "DMA write allowed"})
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if(element.access.includes("HICWRPROT"))
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AvailableOptions.push({name : "MEMCFG_PROT_ALLOWHICWRITE", displayName: "HIC write allowed"})
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AccessConfig.push(
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{
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name : "access_" + ramMacro,
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displayName : element.name + " RAM Access",
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description: "For GSRAM owned by CPU2: this code will be generated on CPU2",
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minSelections: 0,
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options : AvailableOptions,
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default : AvailableOptions.map(a=>a.name)
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})
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}
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}
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}
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);
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/* Section : RAM Initialization */
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device_driverlib_peripheral.MEMCFG_SECT.
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forEach((element, index) =>
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{
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if (!element.name.includes("_ALL"))
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{
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if (Common.isContextCPU1())
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{
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if (element.name.includes("MEMCFG_SECT_GS"))
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InitRAM.push(
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{
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name : "init_" + element.name,
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displayName: element.displayName,
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default : false
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}
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)
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}
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// only GS/LS/D/M/MSG RAMs. check for MEMCFG_SECT_M covers MSGRAM as well
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if ((element.name.includes("MEMCFG_SECT_LS") || element.name.includes("MEMCFG_SECT_D")||
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element.name.includes("MEMCFG_SECT_M")) && (Common.isContextCPU1() || !element.name.includes("CM")))
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{
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InitRAM.push(
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{
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name : "init_" + element.name,
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displayName: element.displayName,
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default : false
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}
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)
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}
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}
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}
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);
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/* Section : Lock Registers */
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device_driverlib_peripheral.MEMCFG_SECT.
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forEach((element, index) =>
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{
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if (!element.name.includes("_ALL"))
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{
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if((element.name.includes("MEMCFG_SECT_M") || element.name.includes("MEMCFG_SECT_D") ||
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element.name.includes("MEMCFG_SECT_LS")) && (Common.isContextCPU1() || !element.name.includes("CM")))
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{
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LockConfig.push(
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{
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name : "lock_" + element.name,
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displayName : "Lock " + element.displayName + " Config Registers",
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options : [
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{name: "NoLock", displayName: "Do not Lock"},
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{name: "Lock", displayName: "Lock"},
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{name: "LockCommit", displayName: "Lock and Commit"},
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],
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default: "NoLock"
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})
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}
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if (Common.isContextCPU1())
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{
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if(element.name.includes("MEMCFG_SECT_GS") && (Common.isContextCPU1() || !element.name.includes("CM")))
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{
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LockConfig.push(
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{
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name : "lock_" + element.name,
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displayName : "Lock " + element.displayName + " Config Registers",
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description: "For GSRAM blocks configured to be owned by CPU2: the code for Initialization, Access Protection, and Lock Configs will be generated on CPU2",
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options : [
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{name: "NoLock", displayName: "Do not Lock"},
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{name: "Lock", displayName: "Lock"},
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{name: "LockCommit", displayName: "Lock and Commit"},
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],
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default: "NoLock"
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})
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}
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}
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}
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}
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);
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/* Section : Access Violation Interrupt */
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device_driverlib_peripheral.MEMCFG_MVIOL. // Controller access violation interrupts
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forEach((element, index) =>
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{
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ViolIntConfig.push(
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{
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name : "int_" + element.name,
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displayName: "Enable " + element.displayName + " violation interrupt",
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default : false
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}
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)
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}
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);
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if(device_driverlib_peripheral.MEMCFG_NMVIOL) // Non-controller access violation interrupts
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{
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device_driverlib_peripheral.MEMCFG_NMVIOL.
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forEach((element, index) =>
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{
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ViolIntConfig.push(
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{
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name : "int_" + element.name,
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displayName: "Enable " + element.displayName + " violation interrupt",
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default : false
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}
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)
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}
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);
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}
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/* Section : CorrErr Interrupt */
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CorrErrIntConfig = [
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{
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name : "errInt_enable",
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displayName: "Enable Correctable Error Interrupt",
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default : false
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},
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{
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name : "errInt_thres",
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displayName: "Threshold for Correctable Error Interrupt",
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default : 0
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},
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]
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staticConfig.push(
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{
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name : "InitRAM",
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displayName : "RAM Initialization",
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longDescription: "Initialize the memory block.\n - MULTICORE NOTE: Initialization code for GSRAMs owned by CPU2 will be generated for CPU2",
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config : InitRAM
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},
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{
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name : "LSRAM_Config",
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displayName : "LSRAM Configuration",
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longDescription: "",
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config : LSRAMOwnerConfig
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}
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)
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if (Common.isContextCPU1())
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{
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staticConfig.push(
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{
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name : "GSRAM_Config",
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displayName : "GSRAM Configuration",
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longDescription: "\n - For GSRAM blocks owned by CPU2: the code for Access Protection and Lock Configs will be generated on CPU2",
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config : GSRAMOwnerConfig
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}
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)
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}
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if(["F2838x", "F2837xD", "F2837xS", "F2807x"].includes(system.deviceData.deviceId))
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{
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staticConfig.push(
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{
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name : "ROM_Config",
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displayName : "ROM Access Configuration",
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longDescription: "",
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config : ROMConfig
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}
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)
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}
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staticConfig.push(
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{
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name : "Access_Config",
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displayName : "Access Protection for RAMs",
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longDescription: "MULTICORE NOTE: Access Protection code for GSRAMs owned by CPU2 will be generated on CPU2",
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config : AccessConfig
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},
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{
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name : "Lock_Config",
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displayName : "Lock RAM Config Registers",
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longDescription: " - Do not lock : Writes to ACCPROT, TEST, INIT and MSEL fields are allowed\n - Lock : Writes to ACCPROT, TEST, INIT and MSEL fields are blocked. Application can unlock it using the function MemCfg_unlockConfig()\n - Lock and commit : Writes to ACCPROT, TEST, INIT and MSEL fields are permanently blocked.\n - MULTICORE NOTE: Lock Config code for GSRAMs owned by CPU2 will be generated on CPU2",
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config : LockConfig
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},
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{
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name : "ViolInt_Config",
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displayName : "Access Violation Interrupt",
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longDescription: "",
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config : ViolIntConfig
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},
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{
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name : "CorrError_Int",
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displayName : "Correctable Error Interrupt",
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longDescription: "",
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config : CorrErrIntConfig
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},
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{
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name : "registerInterrupts",
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displayName: "Register Interrupt Handler",
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default : false
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}
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)
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/* For SYS_ERR interrupt shared across modules */
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var sharedModuleInstances = undefined
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if(["F2838x", "F280013x", "F280015x"].includes(system.deviceData.deviceId))
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{
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sharedModuleInstances = function (inst) {
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if (inst.registerInterrupts)
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{
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return (
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[
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{
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name: "sysErrInt",
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displayName: "Sys Error Interrupt",
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moduleName: "/driverlib/interrupt/interrupt_sys_err.js",
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collapsed: true,
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},
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]
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);
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}
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return []
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}
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}
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function onValidate(inst, validation)
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{
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if(["F2837xS", "F2837xD", "F2807x", "F28004x"].includes(system.deviceData.deviceId))
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var maxThres = 0xFFFFFFFF
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else
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var maxThres = 0xFFFF
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if (inst.errInt_thres > maxThres)
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{
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validation.logError("The threshold value must be less than 0x" + maxThres.toString(16).toUpperCase() + "!", inst, "errInt_thres");
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}
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if (inst.rom_prefetch){
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if (!inst.rom_waitstate){
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validation.logWarning("You must enable ROM wait state to properly use the enable ROM prefetch setting", inst, "rom_waitstate");
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}
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}
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}
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var memcfgModule = {
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peripheralName : "MEMCFG",
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displayName : "MEMCFG",
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longDescription : longDescription,
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maxInstances : 1,
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defaultInstanceName: "myMEMCFG",
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description : "Memory Configuration",
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moduleStatic : {
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config : staticConfig,
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moduleInstances: (inst) => {
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if (inst.registerInterrupts)
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{
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if(!["F2838x", "F280013x", "F280015x"].includes(system.deviceData.deviceId))
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{
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return [
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{
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name: "memcfgAccInt",
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displayName: "Access Violation Interrupt",
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moduleName: "/driverlib/interrupt.js",
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collapsed: true,
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args: {
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$name : "RAM_ACC_VIOL_INT",
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int : "RAM_ACC_VIOL_INT",
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pinmuxPeripheralModule : "",
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driverlibInt: "INT_RAM_ACC_VIOL"
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}
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},
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{
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name: "memcfgCorrErrInt",
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displayName: "Correctable Error Interrupt",
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moduleName: "/driverlib/interrupt.js",
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collapsed: true,
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args: {
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$name : "RAM_CORR_ERR_INT",
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int : "RAM_CORR_ERR_INT",
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pinmuxPeripheralModule : "",
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driverlibInt: "INT_RAM_CORR_ERR"
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}
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}
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]
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}
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}
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return []
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},
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sharedModuleInstances : sharedModuleInstances,
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validate: onValidate,
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},
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templates: {
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boardc: "/driverlib/memcfg/memcfg.board.c.xdt",
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boardh: "/driverlib/memcfg/memcfg.board.h.xdt"
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},
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};
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exports = memcfgModule; |