483 lines
16 KiB
C
483 lines
16 KiB
C
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//#############################################################################
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//
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// FILE: spi_DMA.c
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//
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// TITLE: C28x-SPI source file when using DMA with SPI
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// <h1> C28x-SPI source file when using DMA with SPI </h1>
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//
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//#############################################################################
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//
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//
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// $Copyright:
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// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//#############################################################################
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//
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// Included Files
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//
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#include "driverlib.h"
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#include "device.h"
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#include "spi_DMA.h"
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//Global variables
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uint16_t DMATXbuff[BUFFER_SIZE];
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uint16_t DMARXbuff[BUFFER_SIZE];
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#pragma DATA_SECTION(DMATXbuff, "ramgs0"); // map the TX data to memory
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#pragma DATA_SECTION(DMARXbuff, "ramgs0"); // map the RX data to memory
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struct SPI_DMA_handle SPI_DMA_Handle;
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struct DMA_CH SPITXDMA;
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struct DMA_CH SPIRXDMA;
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void SPI_DMA_ByteTransaction(uint16_t data, struct SPI_DMA_handle *pSPI_DMA_Handle)
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{
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//wordSize for a byte is 8 (because 1 byte = 8 bits)
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uint16_t wordSize = 8U;
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ASSERT(data < (1<<wordSize));
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//Fill the TXbuffer with data to be transmitted
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uint16_t *pbuffer = pSPI_DMA_Handle->pSPITXDMA->pbuffer;
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uint16_t currentpointer = pSPI_DMA_Handle->pSPITXDMA->currentpointer;
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pbuffer[currentpointer++] = data;
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pSPI_DMA_Handle->pSPITXDMA->currentpointer = currentpointer;
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}
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void SPI_DMA_NBytesTransaction(uint16_t *pTXbuffer, uint16_t numOfbytes, struct SPI_DMA_handle *pSPI_DMA_Handle)
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{
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uint16_t *pbuffer = pSPI_DMA_Handle->pSPITXDMA->pbuffer;
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uint16_t currentpointer = pSPI_DMA_Handle->pSPITXDMA->currentpointer;
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uint16_t i=0;
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for(i=0;i<numOfbytes;i++)
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{
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if(pTXbuffer == NULL)
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{
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//Fill the TXbuffer with dummy data to be transmitted
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//Here the dummy data is 0xFFFF
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pbuffer[currentpointer++] = 0xFFFF;
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}
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else
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{
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//Fill the TXbuffer
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pbuffer[currentpointer++] = pTXbuffer[i];
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}
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}
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pSPI_DMA_Handle->pSPITXDMA->currentpointer = currentpointer;
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}
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void SPI_DMA_16bitWordTransaction(uint16_t data, struct SPI_DMA_handle *pSPI_DMA_Handle)
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{
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//wordSize is 16
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uint16_t wordSize = 16U;
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ASSERT(data < ((uint32_t)1<<wordSize));
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//Fill the TXbuffer with data to be transmitted
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uint16_t *pbuffer = pSPI_DMA_Handle->pSPITXDMA->pbuffer;
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uint16_t currentpointer = pSPI_DMA_Handle->pSPITXDMA->currentpointer;
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pbuffer[currentpointer++] = (data & 0xFF00) >> 8;
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pbuffer[currentpointer++] = (data & 0xFF);
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pSPI_DMA_Handle->pSPITXDMA->currentpointer = currentpointer;
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}
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void SPI_DMA_24bitWordTransaction(uint32_t data, struct SPI_DMA_handle *pSPI_DMA_Handle)
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{
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//wordSize is 24
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uint16_t wordSize = 24U;
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ASSERT(data < ((uint32_t)1<<wordSize));
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//Fill the TXbuffer with data to be transmitted
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uint16_t *pbuffer = pSPI_DMA_Handle->pSPITXDMA->pbuffer;
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uint16_t currentpointer = pSPI_DMA_Handle->pSPITXDMA->currentpointer;
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pbuffer[currentpointer++] = (data & 0xFF0000) >> 16U;
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pbuffer[currentpointer++] = (data & 0x00FF00) >> 8U;
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pbuffer[currentpointer++] = (data & 0x0000FF);
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pSPI_DMA_Handle->pSPITXDMA->currentpointer = currentpointer;
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}
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void SPI_DMA_StartTransaction(struct SPI_DMA_handle *pSPI_DMA_Handle, uint16_t charlength, uint16_t txdly)
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{
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uint16_t i = 0;
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ASSERT((charlength >= 1U) && (charlength <= 16U));
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pSPI_DMA_Handle->TransactionStatus = SPI_DMA_TRANSACTION_STARTED;
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uint32_t spibase = pSPI_DMA_Handle->spibase;
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uint32_t dmaTXbase = pSPI_DMA_Handle->pSPITXDMA->dmach;
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uint32_t dmaRXbase = pSPI_DMA_Handle->pSPIRXDMA->dmach;
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uint16_t *pTXbuffer = pSPI_DMA_Handle->pSPITXDMA->pbuffer;
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uint16_t *pRXbuffer = pSPI_DMA_Handle->pSPIRXDMA->pbuffer;
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uint16_t currentpointer = pSPI_DMA_Handle->pSPITXDMA->currentpointer;
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ASSERT(SPI_isBaseValid(spibase));
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uint16_t maxTransactionSize = currentpointer;
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pSPI_DMA_Handle->pSPITXDMA->maxTransactionSize = maxTransactionSize;
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/********************************************************************************/
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// SPI configuration
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/********************************************************************************/
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SPI_setcharLength(spibase, charlength);
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uint16_t TXbuff_pos = 0;
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for(i=1;i<=maxTransactionSize;i++)
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{
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pTXbuffer[TXbuff_pos] = pTXbuffer[TXbuff_pos] << (16 - charlength);
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TXbuff_pos++;
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}
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//Reset the TX / RX FIFO buffers to default state
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SPI_disableFIFO(spibase); //Disable FIFO register
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SPI_enableFIFO(spibase); //Enable FIFO register
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//Configure the FIFO Transmit Delay
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SPI_setTxFifoTransmitDelay(spibase, txdly);
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uint16_t burst_size = 0;
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uint16_t transfer_size = 1;
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//Determine the number of 16-level words from number of words to be transmitted / received
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uint16_t numofSixteenWords = maxTransactionSize / SPI_FIFO_TXFULL;
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//Determine the number of remaining words from number of words to be transmitted / received
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uint16_t remainingWords = maxTransactionSize % SPI_FIFO_TXFULL;
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if(numofSixteenWords)
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{
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SPI_setFIFOInterruptLevel(spibase, SPI_FIFO_TXEMPTY, SPI_FIFO_RXFULL);
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burst_size = 16U;
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transfer_size = numofSixteenWords;
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}
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else
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{
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SPI_setFIFOInterruptLevel(spibase, SPI_FIFO_TXEMPTY, (SPI_RxFIFOLevel)remainingWords);
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burst_size = remainingWords;
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transfer_size = 1;
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}
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SPI_enableInterrupt(spibase, SPI_INT_RXFF);
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// Initialize DMA
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DMA_initController();
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/********************************************************************************/
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// DMA TX Channel configuration
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/********************************************************************************/
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ASSERT(DMA_isBaseValid(dmaTXbase));
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uint32_t dmaTX_IntNum = selectDMA_PIE_Interrupt(dmaTXbase);
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Interrupt_register(dmaTX_IntNum, &dmaTXISR);
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uint16_t *psrcAddr = pTXbuffer;
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uint16_t *pdestAddr = (uint16_t *)(spibase + SPI_O_TXBUF);
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DMA_configAddresses(dmaTXbase, pdestAddr, psrcAddr);
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DMA_configBurst(dmaTXbase, burst_size, 1, 0);
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DMA_configTransfer(dmaTXbase, transfer_size, 1, 0);
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DMA_configMode(dmaTXbase, DMA_TRIGGER_SOFTWARE, DMA_CFG_ONESHOT_DISABLE | DMA_CFG_CONTINUOUS_ENABLE |
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DMA_CFG_SIZE_16BIT);
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DMA_setEmulationMode(DMA_EMULATION_FREE_RUN);
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// DMA SW trigger to start SPI transaction using DMA
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DMA_enableTrigger(dmaTXbase);
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/********************************************************************************/
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// DMA RX Channel configuration
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/********************************************************************************/
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ASSERT(DMA_isBaseValid(dmaRXbase));
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uint32_t dmaRX_IntNum = selectDMA_PIE_Interrupt(dmaRXbase);
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Interrupt_register(dmaRX_IntNum, &dmaRXISR);
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psrcAddr = (uint16_t *)(spibase + SPI_O_RXBUF);
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pdestAddr = pRXbuffer;
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//Enable RXFIFO interrupt to ensure DMA RX channel is triggered
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SPI_enableInterrupt(spibase, SPI_INT_RXFF);
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DMA_configAddresses(dmaRXbase, pdestAddr, psrcAddr);
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DMA_configBurst(dmaRXbase, BURST, 0, 1);
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DMA_configTransfer(dmaRXbase, TRANSFER, 0, 1);
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DMA_configMode(dmaRXbase, DMA_TRIGGER_SPIARX, DMA_CFG_ONESHOT_DISABLE |
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DMA_CFG_CONTINUOUS_ENABLE | DMA_CFG_SIZE_16BIT);
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//
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// Configure DMA RX interrupts
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//
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DMA_setInterruptMode(dmaRXbase, DMA_INT_AT_END);
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DMA_enableInterrupt(dmaRXbase);
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DMA_enableTrigger(dmaRXbase);
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pSPI_DMA_Handle->pSPITXDMA->currentpointer = burst_size;
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pSPI_DMA_Handle->pSPIRXDMA->currentpointer = burst_size;
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//Chip select pulled LOW
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CS_LOW;
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//DMA SW trigger to initiate SPI transaction
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DMA_forceTrigger(dmaTXbase);
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}
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//
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// Function used to select correct dma channel based base address provided
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//
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uint32_t selectDMA_PIE_Interrupt(uint32_t dmachbase)
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{
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uint32_t DMA_Channel = 0;
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switch(dmachbase)
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{
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case DMA_CH1_BASE:
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DMA_startChannel(DMA_CH1_BASE);
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DMA_Channel = INT_DMA_CH1;
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Interrupt_enable(DMA_Channel);
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break;
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case DMA_CH2_BASE:
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DMA_startChannel(DMA_CH2_BASE);
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DMA_Channel = INT_DMA_CH2;
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Interrupt_enable(DMA_Channel);
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break;
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case DMA_CH3_BASE:
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DMA_startChannel(DMA_CH3_BASE);
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DMA_Channel = INT_DMA_CH3;
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Interrupt_enable(DMA_Channel);
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break;
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case DMA_CH4_BASE:
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DMA_startChannel(DMA_CH4_BASE);
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DMA_Channel = INT_DMA_CH4;
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Interrupt_enable(DMA_Channel);
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break;
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case DMA_CH5_BASE:
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DMA_startChannel(DMA_CH5_BASE);
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DMA_Channel = INT_DMA_CH5;
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Interrupt_enable(DMA_Channel);
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break;
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case DMA_CH6_BASE:
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DMA_startChannel(DMA_CH6_BASE);
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DMA_Channel = INT_DMA_CH6;
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Interrupt_enable(DMA_Channel);
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break;
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}
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return(DMA_Channel);
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}
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//
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// DMA TX ISR
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// Not used in this example.
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//
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__interrupt void dmaTXISR(void)
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{
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Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP7);
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return;
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}
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//
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// DMA RX ISR
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//
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__interrupt void dmaRXISR(void)
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{
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uint32_t spibase = SPI_DMA_Handle.spibase;
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uint32_t dmaTXbase = SPI_DMA_Handle.pSPITXDMA->dmach;
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uint32_t dmaRXbase = SPI_DMA_Handle.pSPIRXDMA->dmach;
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uint16_t remainingWords = SPI_DMA_Handle.pSPITXDMA->maxTransactionSize - SPI_DMA_Handle.pSPITXDMA->currentpointer;
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uint16_t burst_size = 0;
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uint16_t srcAddr = HWREGH(dmaTXbase + DMA_O_SRC_ADDR_ACTIVE);
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uint16_t destAddr = HWREGH(dmaRXbase + DMA_O_DST_ADDR_ACTIVE);
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DMA_configSourceAddress(dmaTXbase, (const void *)srcAddr);
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DMA_configDestAddress(dmaRXbase, (const void *)destAddr);
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//If the remainingWords is non-zero and less than FIFO level (16U), then reconfigure
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//DMA burst and RX FIFO level
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if(remainingWords > 0 && remainingWords < 16)
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{
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burst_size = remainingWords;
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SPI_DMA_Handle.pSPITXDMA->currentpointer += remainingWords;
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SPI_setFIFOInterruptLevel(spibase, SPI_FIFO_TXEMPTY, (SPI_RxFIFOLevel)remainingWords);
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DMA_configBurst(dmaTXbase, burst_size, 1, 0);
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DMA_configBurst(dmaRXbase, burst_size, 0, 1);
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}
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if(remainingWords >= 16)
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{
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SPI_DMA_Handle.pSPITXDMA->currentpointer += 16U;
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}
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//If no remainingWords, pull chip select high and stop DMA CH6
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if(remainingWords == 0)
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{
|
||
|
|
CS_HIGH; //Chip select pulled high
|
||
|
|
|
||
|
|
//Reset currentpointer for both TX / RX
|
||
|
|
SPI_DMA_Handle.pSPITXDMA->currentpointer = 0;
|
||
|
|
SPI_DMA_Handle.pSPIRXDMA->currentpointer = 0;
|
||
|
|
|
||
|
|
//Stop both TX / RX DMA channels
|
||
|
|
DMA_stopChannel(dmaTXbase);
|
||
|
|
DMA_stopChannel(dmaRXbase);
|
||
|
|
|
||
|
|
//Increment function pointer to execute next function
|
||
|
|
SPI_DMA_Handle.FunctionCount++;
|
||
|
|
if(SPI_DMA_Handle.TransactionType == SPI_DMA_READ_STATUS_REGISTER)
|
||
|
|
{
|
||
|
|
//Execute the same function until we received expected output
|
||
|
|
if(SPI_DMA_Handle.pSPIRXDMA->pbuffer[SPI_DMA_Handle.offsetRXbuff] != SPI_DMA_Handle.expectedOutput)
|
||
|
|
{
|
||
|
|
SPI_DMA_Handle.FunctionCount--;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if(SPI_DMA_Handle.TransactionType == SPI_DMA_READ_TRANSACTION)
|
||
|
|
{
|
||
|
|
uint16_t numRXbytes = SPI_DMA_Handle.pSPITXDMA->maxTransactionSize - SPI_DMA_Handle.offsetRXbuff;
|
||
|
|
|
||
|
|
int16_t i = numRXbytes-1;
|
||
|
|
uint16_t *pReceiveBuffer = SPI_DMA_Handle.pSPIRXDMA->pbuffer + SPI_DMA_Handle.offsetRXbuff;
|
||
|
|
SPI_DMA_Handle.pSPIRXDMA->pbuffer = pReceiveBuffer;
|
||
|
|
|
||
|
|
//When the number of RXbytes is less than 4
|
||
|
|
//package data into RX data based on endianess
|
||
|
|
while(i>=0 && numRXbytes<=4)
|
||
|
|
{
|
||
|
|
if(SPI_DMA_Handle.endianess == SPI_DATA_BIG_ENDIAN)
|
||
|
|
{
|
||
|
|
SPI_DMA_Handle.RXdata |= (uint32_t)pReceiveBuffer[i] << (i * SPI_DMA_Handle.charlength);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
SPI_DMA_Handle.RXdata |= (uint32_t)pReceiveBuffer[numRXbytes-i-1] << (i * SPI_DMA_Handle.charlength);
|
||
|
|
}
|
||
|
|
i--;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
//If function pointer in not equal to NULL.
|
||
|
|
//Execute next function
|
||
|
|
if(SPI_DMA_Handle.pFunction[SPI_DMA_Handle.FunctionCount] != NULL)
|
||
|
|
{
|
||
|
|
SPI_DMA_Handle.pFunction[SPI_DMA_Handle.FunctionCount]();
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
SPI_DMA_Handle.TransactionStatus = SPI_DMA_TRANSACTION_COMPLETE;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{ //We still have remaining transactions
|
||
|
|
DMA_forceTrigger(dmaTXbase);
|
||
|
|
}
|
||
|
|
|
||
|
|
//Acknowledge CPU interrupt flag
|
||
|
|
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP7);
|
||
|
|
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// Function used to update SPI_DMA_Handle function pointer
|
||
|
|
// and start executing first function in function pointer array
|
||
|
|
//
|
||
|
|
void RunCommandSequence(functionPointer *pFunction)
|
||
|
|
{
|
||
|
|
SPI_DMA_Handle.FunctionCount = 0;
|
||
|
|
|
||
|
|
uint16_t i;
|
||
|
|
//Fill function pointer array in SPI_DMA_Handle
|
||
|
|
for(i=0;i<5U;i++)
|
||
|
|
{
|
||
|
|
SPI_DMA_Handle.pFunction[i] = *pFunction[i];
|
||
|
|
}
|
||
|
|
|
||
|
|
//Execute the first function in function pointer array
|
||
|
|
SPI_DMA_Handle.pFunction[0]();
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// Function used to update SPI_DMA_Handle parameters
|
||
|
|
//
|
||
|
|
void setupSPI_DMA_Handler(uint32_t spibase, uint16_t charlength, uint32_t dmaTXbase, uint32_t dmaRXbase)
|
||
|
|
{
|
||
|
|
|
||
|
|
///////////////////////////////////////////
|
||
|
|
// SPI configuration //
|
||
|
|
///////////////////////////////////////////
|
||
|
|
SPI_DMA_Handle.spibase = spibase;
|
||
|
|
SPI_DMA_Handle.charlength = charlength;
|
||
|
|
SPI_DMA_Handle.pSPITXDMA = &SPITXDMA;
|
||
|
|
SPI_DMA_Handle.pSPIRXDMA = &SPIRXDMA;
|
||
|
|
|
||
|
|
///////////////////////////////////////////
|
||
|
|
// DMA Transmit channel configuration //
|
||
|
|
///////////////////////////////////////////
|
||
|
|
SPITXDMA.dmach = dmaTXbase;
|
||
|
|
SPITXDMA.pbuffer = &DMATXbuff[0];
|
||
|
|
SPITXDMA.currentpointer = 0;
|
||
|
|
|
||
|
|
///////////////////////////////////////////
|
||
|
|
// DMA Receive channel configuration //
|
||
|
|
///////////////////////////////////////////
|
||
|
|
SPIRXDMA.dmach = dmaRXbase;
|
||
|
|
SPIRXDMA.pbuffer = &DMARXbuff[0];
|
||
|
|
SPIRXDMA.currentpointer = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
|