374 lines
12 KiB
Plaintext
374 lines
12 KiB
Plaintext
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%let clocktree_common = system.getScript("/driverlib/.meta/clocktree/clocktree_common.js");
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%let Common = system.getScript("/driverlib/Common.js");
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%
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%var DualCore = clocktree_common.DualCore;
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%var SingleCore = clocktree_common.SingleCore;
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%
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%const multi_core = clocktree_common.multi_core;
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%const PLL_type1 = clocktree_common.PLL_type1;
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%const PLL_type2 = clocktree_common.PLL_type2;
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%
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%const device = clocktree_common.device;
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%
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%var otherTree = Common.getClockTree();
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% if (otherTree!=null){ // If we can't get clock tree, CPU1 context is probably not open
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%const AUXPLL_Support = clocktree_common.AUXPLL_Support;
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%const EPWM_div_support = clocktree_common.EPWM_div_support;
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%const xtal_x1_macro = clocktree_common.xtal_x1_macro;
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%var XTAL_OR_X1 = clocktree_common.XTAL_OR_X1;
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%
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%//////////////////////////////////////////////////
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%// Frequency lables
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%//////////////////////////////////////////////////
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%const OSCCLK_d = otherTree.OSCCLK.in
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%const PLLRAWCLK_d = otherTree.PLLRAWCLK.in
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%const PLLSYSCLK_d = otherTree.PLLSYSCLK.in
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%const CPU1_CPUCLK_d = otherTree.CPU1_CPUCLK.in
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%const CPU2_CPUCLK_d = otherTree.CPU2_CPUCLK.in
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%const CPU1_SYSCLK_d = otherTree.CPU1_SYSCLK.in
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%const CPU2_SYSCLK_d = otherTree.CPU2_SYSCLK.in
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%const LSPCLK_d = otherTree.LSPCLK.in
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%
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%//////////////////////////////////////////////////
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%// OSCCLK source
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%//////////////////////////////////////////////////
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%
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%var OSCCLKSRCSEL = otherTree.OSCCLKSRCSEL
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%
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%var oscclkSrc = "SYSCTL_OSCSRC_OSC2"
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%var oscclksource
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%var oscclk = 10
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%
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%//////////////////////////////////////////////////
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%// IMULT, FMULT (PLLRAWCLK) source
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%//////////////////////////////////////////////////
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%
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%var SYSPLLCTL1 = otherTree.SYSPLLCTL1
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%
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%var PLL_IMULT_mv = otherTree.PLL_IMULT.multiplyValue
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%var PLL_IMULT = "SYSCTL_IMULT(" + PLL_IMULT_mv + ")"
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%
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%var SYSCLKDIVSEL_dv = otherTree.SYSCLKDIVSEL.divideValue
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%
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%var PLL_DIVSEL = "SYSCTL_SYSDIV(" + SYSCLKDIVSEL_dv + ")"
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%
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%var PLL_FMULT
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%if(PLL_type1.includes(device))
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%{
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%var PLL_FMULT_mv = otherTree.PLL_FMULT.multiplyValue
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% switch(PLL_FMULT_mv){
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% case 0:
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% PLL_FMULT = "SYSCTL_FMULT_NONE"
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% break
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% case 0.25:
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% PLL_FMULT = "SYSCTL_FMULT_1_4"
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% break
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% case 0.5:
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% PLL_FMULT = "SYSCTL_FMULT_1_2"
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% break
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% case 0.75:
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% PLL_FMULT = "SYSCTL_FMULT_3_4"
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% break
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% }
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%}
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%
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%var PLL_STS = 'SYSCTL_PLL_ENABLE'
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%var SYSPLL_STS = 'DISABLED'
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%
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%if(SYSPLLCTL1.inputSelect == 'OSCCLK')
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%{
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% PLL_STS = 'SYSCTL_PLL_DISABLE'
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% SYSPLL_STS = 'DISABLED'
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%}
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%else
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%{
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% PLL_STS = 'SYSCTL_PLL_ENABLE'
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% SYSPLL_STS = 'ENABLED'
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%}
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%
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%
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%if(PLL_type2.includes(device))
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%{
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% var PLL_REFDIV_dv = otherTree.PLL_REFDIV.divideValue
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% var PLL_REFDIV = "SYSCTL_REFDIV(" + PLL_REFDIV_dv + ")"
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%
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% var PLL_ODIV_dv = otherTree.PLL_ODIV.divideValue
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% var PLL_ODIV = "SYSCTL_ODIV(" + PLL_ODIV_dv + ")"
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%}
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%
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%//////////////////////////////////////////////////
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%// Frequency lables
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%//////////////////////////////////////////////////
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%const AUXOSCCLK_d = otherTree.AUXOSCCLK.in
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%const AUXPLLRAWCLK_d = otherTree.AUXPLLRAWCLK.in
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%const AUXPLLCLK_d = otherTree.AUXPLLCLK.in
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%
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%//////////////////////////////////////////////////
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%// AUXOSCCLK source
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%//////////////////////////////////////////////////
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%
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%var AUXOSCCLKSRCSEL = otherTree.AUXOSCCLKSRCSEL
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%
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%var auxoscclkSrc = "SYSCTL_OSCSRC_OSC2"
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%var auxoscclksource
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%var auxoscclk = 10
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%
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%
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%//////////////////////////////////////////////////
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%// IMULT, FMULT (AUXRAWCLK) source
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%//////////////////////////////////////////////////
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%
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%
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%var AUX_PLLEN = otherTree.AUX_PLLEN
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%var AUX_IMULT_mv = otherTree.AUX_IMULT.multiplyValue
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%var AUX_IMULT = "SYSCTL_AUXPLL_IMULT(" + AUX_IMULT_mv + ")"
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%
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%var AUXCLKDIVSEL_dv = otherTree.AUXCLKDIVSEL.divideValue
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%
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%var AUX_DIVSEL = "SYSCTL_AUXPLL_DIV_" + AUXCLKDIVSEL_dv
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%
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%
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%var AUX_FMULT
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%if(PLL_type1.includes(device))
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%{
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% var AUX_FMULT_mv = otherTree.AUX_FMULT.multiplyValue
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% switch(otherTree.AUX_FMULT.multiplyValue){
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% case 0:
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% AUX_FMULT = "SYSCTL_AUXPLL_FMULT_NONE"
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% break
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% case 0.25:
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% AUX_FMULT = "SYSCTL_AUXPLL_FMULT_1_4"
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% break
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% case 0.5:
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% AUX_FMULT = "SYSCTL_AUXPLL_FMULT_1_2"
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% break
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% case 0.75:
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% AUX_FMULT = "SYSCTL_AUXPLL_FMULT_3_4"
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% }
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%}
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%
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%if(PLL_type2.includes(device))
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%{
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% var AUX_REFDIV_dv = otherTree.AUX_REFDIV.divideValue
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% var AUX_REFDIV = "SYSCTL_REFDIV(" + AUX_REFDIV_dv + ")"
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%
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% var AUX_ODIV_dv = otherTree.AUX_ODIV.divideValue
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% var AUX_ODIV = "SYSCTL_ODIV(" + AUX_ODIV_dv + ")"
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%
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% var AUXCLKDIVSEL_dv = otherTree.AUXCLKDIVSEL.divideValue
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%}
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%
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%var AUXPLL_STS = 'SYSCTL_AUXPLL_ENABLE'
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%var AUXPLL_Status = 'DISABLED'
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%
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%if(AUX_PLLEN.inputSelect == 'AUXOSCCLK')
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%{
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% AUXPLL_STS = 'SYSCTL_AUXPLL_DISABLE'
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% AUXPLL_Status = 'DISABLED'
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%}
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%else
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%{
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% AUXPLL_STS = 'SYSCTL_AUXPLL_ENABLE'
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% AUXPLL_Status = 'ENABLED'
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%}
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%
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%
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%/////////////////////////////////////////////////////////////////////////////////////////
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%
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%
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//#############################################################################
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//
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// FILE: clockTree.h
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//
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// TITLE: Setups device clocking for CPU2 for examples.
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//
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//#############################################################################
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// $Copyright:
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// Copyright (C) `new Date().getFullYear()` Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef CLOCKTREE_H
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#define CLOCKTREE_H
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//*****************************************************************************
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//
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// Summary of SYSPLL related clock configuration
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//
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//*****************************************************************************
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//
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// Input Clock to SYSPLL (OSCCLK) = `OSCCLK_d` MHz (`oscclksource` provides OSCCLK)
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//
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//##### SYSPLL `SYSPLL_STS` #####
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//
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// PLLRAWCLK = `PLLRAWCLK_d` MHz (Output of SYSPLL if enabled)
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// PLLSYSCLK = `PLLSYSCLK_d` MHz
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// CPU1CLK = `CPU1_CPUCLK_d` MHz
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// CPU2CLK = `CPU2_CPUCLK_d` MHz
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// CPU1_SYSCLK = `CPU1_SYSCLK_d` MHz
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// CPU2_SYSCLK = `CPU2_SYSCLK_d` MHz
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// LSPCLK = `LSPCLK_d` MHz
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%
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%if(EPWM_div_support.includes(device))
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%{
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% var EPWMCLK_d = otherTree.PLLSYSCLK.in / otherTree.EPWMCLKDIV.divideValue
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// EPWMCLK = `EPWMCLK_d` MHz
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%}
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//*****************************************************************************
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//
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// Macro definitions used in device.c (SYSPLL / LSPCLK)
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//
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//*****************************************************************************
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//
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// Input Clock to SYSPLL (OSCCLK) = `oscclksource` = `OSCCLK_d` MHz
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//
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#define DEVICE_OSCSRC_FREQ `OSCCLK_d`000000U
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%
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% /////////////////////////////////////////////////////////////////////////////////////////
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%
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% if(PLL_type1.includes(device))
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% {
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//
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// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
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%if(PLL_STS == 'SYSCTL_PLL_ENABLE')
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% {
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// SYSPLL ENABLED
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// SYSCLK = `PLLSYSCLK_d` MHz = `OSCCLK_d` MHz (OSCCLK) * (`PLL_IMULT_mv` (IMULT) + `PLL_FMULT_mv` (FMULT)) / `SYSCLKDIVSEL_dv` (SYSCLKDIVSEL)
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#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * (`PLL_IMULT_mv` + `PLL_FMULT_mv`)) / `SYSCLKDIVSEL_dv`)
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% }
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%else
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% {
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// SYSPLL DISABLED
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// SYSCLK = `OSCCLK_d` MHz(`oscclksource`) / `SYSCLKDIVSEL_dv` (SYSCLKDIVSEL) = `PLLSYSCLK_d` MHz
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#define DEVICE_SYSCLK_FREQ (DEVICE_OSCSRC_FREQ / `SYSCLKDIVSEL_dv`)
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% }
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%}
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% /////////////////////////////////////////////////////////////////////////////////////////
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%
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% if(PLL_type2.includes(device))
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% {
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//
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// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
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%if(PLL_STS == 'SYSCTL_PLL_ENABLE')
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% {
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// SYSPLL ENABLED
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// SYSCLK = `PLLSYSCLK_d` MHz = `OSCCLK_d` MHz (OSCCLK) * `PLL_IMULT_mv` (IMULT) / (`PLL_REFDIV_dv` (REFDIV) * `PLL_ODIV_dv` (ODIV) * `SYSCLKDIVSEL_dv` (SYSCLKDIVSEL))
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% }
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%else
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% {
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// SYSPLL DISABLED
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// SYSCLK = `OSCCLK_d` MHz(`oscclksource`) / `SYSCLKDIVSEL_dv` (SYSCLKDIVSEL) = `PLLSYSCLK_d` MHz
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% }
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#define DEVICE_SYSCLK_FREQ (DEVICE_OSCSRC_FREQ * `PLL_IMULT_mv`) / (`PLL_REFDIV_dv` * `PLL_ODIV_dv` * `SYSCLKDIVSEL_dv`)
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% }
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% /////////////////////////////////////////////////////////////////////////////////////////
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//
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// Define to pass to SysCtl_setLowSpeedClock().
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// Low Speed Clock (LSPCLK) = `PLLSYSCLK_d` MHz / `otherTree.LOSPCP.divideValue` = `LSPCLK_d` MHz
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//
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#define DEVICE_LSPCLK_CFG SYSCTL_LSPCLK_PRESCALE_`otherTree.LOSPCP.divideValue`
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#define DEVICE_LSPCLK_FREQ (DEVICE_SYSCLK_FREQ / `otherTree.LOSPCP.divideValue`)
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//*****************************************************************************
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//
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// Summary of AUXPLL related clock configuration
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//
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//*****************************************************************************
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//
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// Input Clock to AUXOSCCLK = `AUXOSCCLK_d` MHz (`auxoscclksource` provides AUXOSCCLK)
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//
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//##### AUXPLL `AUXPLL_Status` #####
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//
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// AUXPLLRAWCLK = `AUXPLLRAWCLK_d` MHz (Output of AUXPLL if enabled)
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// AUXPLLCLK = `AUXPLLCLK_d` MHz
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//
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//*****************************************************************************
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//
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// Macro definitions used in device.c (AUXPLL)
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//
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//*****************************************************************************
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//
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// Input Clock to AUXPLL (AUXOSCCLK) = `auxoscclksource` = `AUXOSCCLK_d` MHz
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//
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#define DEVICE_AUXOSCSRC_FREQ `AUXOSCCLK_d`000000U
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%
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% if(PLL_type1.includes(device))
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% {
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//
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// Define to pass to SysCtl_setAuxClock(). Will configure the clock as follows:
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%if(AUXPLL_STS == 'SYSCTL_AUXPLL_ENABLE')
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% {
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// AUXPLL ENABLED
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// AUXPLLCLK = `AUXPLLCLK_d` MHz = `AUXOSCCLK_d` MHz (AUXOSCCLK) * (`AUX_IMULT_mv` (AUX_IMULT) + `AUX_FMULT_mv` (AUX_FMULT)) / `AUXCLKDIVSEL_dv` (AUXCLKDIVSEL)
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#define DEVICE_AUXCLK_FREQ ((DEVICE_AUXOSCSRC_FREQ * (`AUX_IMULT_mv` + `AUX_FMULT_mv`)) / `AUXCLKDIVSEL_dv`)
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% }
|
||
|
|
%else
|
||
|
|
% {
|
||
|
|
// AUXPLL DISABLED
|
||
|
|
// AUXPLLCLK = `AUXPLLCLK_d` MHz = `AUXOSCCLK_d` MHz (`auxoscclksource`) / `AUXCLKDIVSEL_dv` (AUXCLKDIVSEL)
|
||
|
|
#define DEVICE_AUXCLK_FREQ (DEVICE_AUXOSCSRC_FREQ / `AUXCLKDIVSEL_dv`)
|
||
|
|
% }
|
||
|
|
//
|
||
|
|
% }
|
||
|
|
%
|
||
|
|
% if(PLL_type2.includes(device))
|
||
|
|
% {
|
||
|
|
//
|
||
|
|
// Define to pass to SysCtl_setAuxClock(). Will configure the clock as follows:
|
||
|
|
%if(AUXPLL_STS == 'SYSCTL_AUXPLL_ENABLE')
|
||
|
|
% {
|
||
|
|
// AUXPLL ENABLED
|
||
|
|
// AUXPLLCLK = `AUXPLLCLK_d` MHz = `AUXOSCCLK_d` MHz (AUXOSCCLK) * `AUX_IMULT_mv` (IMULT) / (`AUX_REFDIV_dv` (REFDIV) * `AUX_ODIV_dv` (ODIV) * `AUXCLKDIVSEL_dv` (AUXCLKDIVSEL))
|
||
|
|
#define DEVICE_AUXCLK_FREQ (DEVICE_OSCSRC_FREQ * `AUX_IMULT_mv`) / (`AUX_REFDIV_dv` * `AUX_ODIV_dv` * `AUXCLKDIVSEL_dv`)
|
||
|
|
% }
|
||
|
|
%else
|
||
|
|
% {
|
||
|
|
// AUXPLL DISABLED
|
||
|
|
// AUXPLLCLK = `AUXPLLCLK_d` MHz = (`AUXOSCCLK_d`) / `AUXCLKDIVSEL_dv` (AUXCLKDIVSEL)
|
||
|
|
#define DEVICE_AUXCLK_FREQ (DEVICE_AUXOSCSRC_FREQ / `AUXCLKDIVSEL_dv`)
|
||
|
|
% }
|
||
|
|
|
||
|
|
% }
|
||
|
|
#endif // CLOCKTREE_H
|
||
|
|
%} else {
|
||
|
|
#ifndef CLOCKTREE_H
|
||
|
|
#define CLOCKTREE_H
|
||
|
|
|
||
|
|
//
|
||
|
|
// CANNOT ACCESS CLOCKTREE. PLEASE MAKE SURE TO OPEN BOTH CPU1 AND CPU2 in SYSCONFIG.
|
||
|
|
//
|
||
|
|
|
||
|
|
#endif // CLOCKTREE_H
|
||
|
|
%}
|