148 lines
4.4 KiB
C
148 lines
4.4 KiB
C
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#ifndef _FPU_H_
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#define _FPU_H_
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//#############################################################################
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//! \file fpu.h
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//!
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//! \brief FPU Register Definitions
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//! \author Vishal Coelho
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//! \date Dec 25, 2012
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//
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// Group: C2000
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//
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//#############################################################################
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//
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//
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// $Copyright: Copyright (C) 2022 Texas Instruments Incorporated -
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// http://www.ti.com/ ALL RIGHTS RESERVED $
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//#############################################################################
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//*****************************************************************************
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// includes
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//*****************************************************************************
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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//*****************************************************************************
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// typedefs
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//*****************************************************************************
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typedef union{
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float f32;
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int32_t i32;
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}R32;
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typedef union{
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#ifdef __TI_EABI__
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double f64;
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#else
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long double f64;
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#endif
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int64_t i64;
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struct {
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R32 L;
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R32 H;
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}half;
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}R64;
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//*****************************************************************************
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// defines
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//*****************************************************************************
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// masks for the status flag bits
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#define MASK_LVF (1 << 0 )
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#define MASK_LUF (1 << 1 )
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#define MASK_NF (1 << 2 )
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#define MASK_ZF (1 << 3 )
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#define MASK_NI (1 << 4 )
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#define MASK_ZI (1 << 5 )
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#define MASK_TF (1 << 6 )
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#define MASK_RNDF32 (1 << 9 )
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#define MASK_RNDF64 (1 << 10)
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#define MASK_SHDWS (1 << 31)
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//! \brief RB register
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//
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struct RB_BITS { // bits description
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uint16_t _RC; //!< 15:0 Repeat Count
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uint16_t _RE:7; //!< 22:16 Repeat Block End Address
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uint16_t _RSIZE:7; //!< 29:23 Repeat Block Size
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uint16_t _RA:1; //!< 30 Repeat Block Active
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uint16_t _RAS:1; //!< 31 Repeat Block Active Shadow
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};
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union RB_REG {
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uint32_t all;
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struct RB_BITS bit;
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};
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//! \brief FPU status register
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//
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struct STF_BITS { // bits description
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uint16_t LVF:1; //!< 0 Latched Overflow Float flag bit
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uint16_t LUF:1; //!< 1 Latched underflow float flag bit
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uint16_t NF:1; //!< 2 Negative float flag bit
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uint16_t ZF:1; //!< 3 Zero float flag bit
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uint16_t NI:1; //!< 4 Negative integer flag bit
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uint16_t ZI:1; //!< 5 Zero integer flag bit
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uint16_t TF:1; //!< 6 Test flag bit
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uint16_t rsvd1:2; //!< 8:7 reserved
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uint16_t RNDF32:1; //!< 9 Round f32 mode
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uint16_t RNDF64:1; //!< 10 Round f64 mode
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uint16_t rsvd2:5; //!< 15:11 reserved
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uint16_t rsvd3:15; //!< 30:16 reserved
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uint16_t SHDWS:1; //!< 31 Shadow mode status bit
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};
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union STF_REG {
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uint32_t all;
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struct STF_BITS bit;
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};
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//! \brief FPU register space
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//! \note
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//! - The registers are mapped to data space only (like peripherals on C28x devices). Program
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//! space data reads or writes are ignored. debug reads/writes work
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//! - All registers are reset to zero on system reset (SYSRSn).
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//! - The RB register is part of the C28-CPI core but is made visible (read only to CPU) in the
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//! memory map. Refer to "CPI Specification" for more details.
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struct FPU_REG{
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union RB_REG _RB;
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union STF_REG _STF;
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uint32_t rsvd1[6];
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R64 _R0;
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R64 _R1;
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R64 _R2;
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R64 _R3;
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R64 _R4;
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R64 _R5;
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R64 _R6;
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R64 _R7;
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// uint32_t _R0L;
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// uint32_t _R0H;
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// uint32_t _R1L;
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// uint32_t _R1H;
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// uint32_t _R2L;
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// uint32_t _R2H;
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// uint32_t _R3L;
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// uint32_t _R3H;
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// uint32_t _R4L;
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// uint32_t _R4H;
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// uint32_t _R5L;
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// uint32_t _R5H;
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// uint32_t _R6L;
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// uint32_t _R6H;
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// uint32_t _R7L;
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// uint32_t _R7H;
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uint32_t rsvd2[104];
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};
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extern volatile struct FPU_REG FpuRegs;
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#ifdef __cplusplus
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}
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#endif // extern "C"
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#endif //end of _FPU_H_ definition
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