466 lines
29 KiB
JSON
466 lines
29 KiB
JSON
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/*
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* Copyright (c) 2018-2020 Texas Instruments Incorporated - http://www.ti.com
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*
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* ======== LAUNCHXL_F2800157.syscfg.json ========
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* Board schematic: [FILL IN WHEN AVAILABLE]
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*/
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{
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"name" : "LAUNCHXL-F2800157",
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"displayName" : "LaunchPad F2800157",
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"device" : "F280015x",
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"part" : "F280015x_80PN",
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"package" : "80PN",
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"headers" : [
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{
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"type": "BoosterPack 40 pin",
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"default": true,
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"name": "boosterpack1",
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"displayName": "BoosterPack1 Standard Header (Top)",
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"dimensions": {
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"columns": [
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{ "top": 1, "bottom": 10 },
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{ "top": 21, "bottom": 30 },
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{ "blank": true },
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{ "top": 40, "bottom": 31 },
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{ "top": 20, "bottom": 11 }
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]
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},
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"pins": [
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{ "number" : 1, "name" : "3V3" },
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{ "number" : 2, "ball": "11", "name" : "ADCINC6" },
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{ "number" : 3, "ball": "4", "name" : "GPIO28_BP" },
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{ "number" : 4, "ball": "3", "name" : "GPIO29_BP" },
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{ "number" : 5, "ball": "3", "name" : "GPIO29_BP" },
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{ "number" : 6, "name" : "" },
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{ "number" : 7, "ball": "75", "name" : "GPIO9_SPI_CLK1" },
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{ "number" : 8, "ball": "41", "name" : "GPIO24" },
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{ "number" : 9, "ball": "50", "name" : "GPIO18_BP" },
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{ "number" : 10, "ball": "51", "name" : "GPIO19_BP" },
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{ "number" : 11, "ball": "38", "name" : "GPIO33_BP" },
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{ "number" : 12, "ball": "43", "name" : "GPIO26_BP" },
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{ "number" : 13, "ball": "69", "name" : "GPIO44" },
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{ "number" : 14, "ball": "76", "name" : "GPIO10_SPI_SOMI1" },
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{ "number" : 15, "ball": "58", "name" : "GPIO8_SPI_SIMO1" },
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{ "number" : 16, "ball": "5", "name" : "XRSn" },
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{ "number" : 17, "ball": "79", "name" : "GPIO14_BP" },
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{ "number" : 18, "ball": "49", "name" : "GPIO32" },
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{ "number" : 19, "ball": "37", "name" : "GPIO11" },
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{ "number" : 20, "name" : "GND" },
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{ "number" : 21, "name" : "5V" },
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{ "number" : 22, "name" : "GND" },
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{ "number" : 23, "ball": "10", "name" : "ADCINA6" },
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{ "number" : 24, "ball": "12", "name" : "ADCINA3/C5" },
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{ "number" : 25, "ball": "13", "name" : "ADCINA2/C9" },
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{ "number" : 26, "ball": "14", "name" : "ADCINA15/C7" },
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{ "number" : 27, "ball": "15", "name" : "ADCINA14/C4" },
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{ "number" : 28, "ball": "16", "name" : "ADCINA11/C0" },
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{ "number" : 29, "ball": "22", "name" : "ADCINA12/C1" },
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{ "number" : 30, "ball": "67", "name" : "GPIO22_PWM_DAC" },
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{ "number" : 31, "name" : "" },
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{ "number" : 32, "ball": "34", "name" : "GPIO21_BP" },
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{ "number" : 33, "ball": "32", "name" : "GPIO49" },
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{ "number" : 34, "ball": "31", "name" : "GPIO48" },
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{ "number" : 35, "ball": "78", "name" : "GPIO15" },
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{ "number" : 36, "ball": "63", "name" : "GPIO0" },
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{ "number" : 37, "ball": "60", "name" : "GPIO3" },
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{ "number" : 38, "ball": "61", "name" : "GPIO2" },
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{ "number" : 39, "ball": "62", "name" : "GPIO1" },
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{ "number" : 40, "ball": "1", "name" : "GPIO30" }
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]
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},
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{
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"type": "BoosterPack 40 pin",
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"default": true,
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"name": "boosterpack2",
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"displayName": "BoosterPack2 Standard Header (Bottom)",
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"dimensions": {
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"columns": [
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{ "top": 41, "bottom": 50 },
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{ "top": 61, "bottom": 70 },
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{ "blank": true },
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{ "top": 80, "bottom": 71 },
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{ "top": 60, "bottom": 51 }
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]
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},
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"pins": [
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{ "number" : 41, "name" : "3V3" },
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{ "number" : 42, "ball": "18", "name" : "ADCINA1" },
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{ "number" : 43, "ball": "65", "name" : "GPIO23_BP" },
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{ "number" : 44, "ball": "64", "name" : "GPIO40_BP" },
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{ "number" : 45, "ball": "64", "name" : "GPIO40_BP" },
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{ "number" : 46, "ball": "", "name" : "" },
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{ "number" : 47, "ball": "75", "name" : "GPIO9_SPI_CLK2" },
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{ "number" : 48, "ball": "73", "name" : "GPIO45" },
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{ "number" : 49, "ball": "66", "name" : "GPIO41" },
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{ "number" : 50, "ball": "77", "name" : "GPIO34" },
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{ "number" : 51, "ball": "6", "name" : "GPIO46" },
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{ "number" : 52, "ball": "54", "name" : "GPIO43_BP" },
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{ "number" : 53, "ball": "48", "name" : "GPIO35" },
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{ "number" : 54, "ball": "76", "name" : "GPIO10_SPI_SOMI2" },
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{ "number" : 55, "ball": "58", "name" : "GPIO8_SPI_SIMO2" },
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{ "number" : 56, "ball": "5", "name" : "XRSn" },
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{ "number" : 57, "ball": "33", "name" : "GPIO20_BP" },
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{ "number" : 58, "ball": "42", "name" : "GPIO25" },
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{ "number" : 59, "ball": "46", "name" : "GPIO37" },
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{ "number" : 60, "name" : "GND" },
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{ "number" : 61, "name" : "5V" },
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{ "number" : 62, "name" : "GND" },
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{ "number" : 63, "ball": "17", "name" : "ADCINA5/C2" },
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{ "number" : 64, "ball": "23", "name" : "ADCINA7/C3" },
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{ "number" : 65, "ball": "24", "name" : "ADCINA8/C11" },
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{ "number" : 66, "ball": "27", "name" : "ADCINA4/C14" },
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{ "number" : 67, "ball": "28", "name" : "ADCINA9/C8" },
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{ "number" : 68, "ball": "29", "name" : "ADCINA10/C10" },
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{ "number" : 69, "ball": "19", "name" : "ADCINA0/C15" },
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{ "number" : 70, "ball": "2", "name" : "GPIO31_PWM_DAC" },
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{ "number" : 71, "ball": "74", "name" : "GPIO5_BP" },
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{ "number" : 72, "ball": "59", "name" : "GPIO4_BP" },
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{ "number" : 73, "ball": "57", "name" : "GPIO42" },
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{ "number" : 74, "ball": "44", "name" : "GPIO27" },
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{ "number" : 75, "ball": "40", "name" : "GPIO17" },
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{ "number" : 76, "ball": "39", "name" : "GPIO16" },
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{ "number" : 77, "ball": "68", "name" : "GPIO7" },
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{ "number" : 78, "ball": "80", "name" : "GPIO6" },
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{ "number" : 79, "ball": "35", "name" : "GPIO13" },
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{ "number" : 80, "ball": "36", "name" : "GPIO12" }
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]
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},
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{
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// "J12 - QEP1 Header",
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"type": "Header",
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"default": true,
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"name": "qepA",
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"displayName": "Header - QEPA",
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"dimensions": {
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"columns": [
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{ "top": 1, "bottom": 5 }
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]
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},
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"pins": [
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{ "number": 1, "ball": "33", "name": "EQEP1A" },
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{ "number": 2, "ball": "34", "name": "EQEP1B" },
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{ "number": 3, "ball": "54", "name": "EQEP1I" },
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{ "number": 4, "name": "5V" },
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{ "number": 5, "name": "GND" }
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]
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},
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{
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// "J13 - QEP2 Header",
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"type": "Header",
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"default": true,
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"name": "qepB",
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"displayName": "Header - QEPB",
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"dimensions": {
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"columns": [
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{ "top": 1, "bottom": 5 }
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]
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},
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"pins": [
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{ "number": 1, "ball": "79", "name": "EQEP2A" },
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{ "number": 2, "ball": "38", "name": "EQEP2B" },
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{ "number": 3, "ball": "43", "name": "EQEP2I" },
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{ "number": 4, "name": "5V" },
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{ "number": 5, "name": "GND" }
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]
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}
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],
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"components": {
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"LED4": {
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"displayName" : "LED4 (User LEDs)",
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"definition" : "/boards/components/led.json",
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"connections" : {
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"OUTPUT": "48" /* GPIO35 */
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}
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},
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"LED5": {
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"displayName" : "LED5 (User LEDs)",
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"definition" : "/boards/components/led.json",
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"connections" : {
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"OUTPUT": "32" /* GPIO49 */
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}
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},
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"D1": {
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"link": "LED4"
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},
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"D2": {
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"link": "LED5"
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},
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"BP_SITE_1": {
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"displayName": "Site 1 Standard BP",
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"description": "Standard BoosterPack (BP) module locations on Site 1 of LaunchPad",
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"longDescription": "All TI LaunchPads follow standard BoosterPack (BP) locations to ensure compatibility with BoosterPack peripherals. Site 1 on this LaunchPad features standard locations for three EPWM signals, I2C, SCI, and SPI.",
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"subComponents": {
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"SCI": {
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"displayName": "SCIA BP",
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"description": "SCIA BoosterPack (BP) location on Site 1",
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"longDescription": "Site 1 of this LaunchPad features standard locations for SCI_RX and SCI_TX. Add this component to make use of the standard SCI BoosterPack (BP) signal locations.\n\n Note: Ensure that the on-board SCI switch is in the correct configuration to route SCIA to the BoosterPack headers.",
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"definition" : "/boards/components/standard_sci.json",
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"connections" : {
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"SCI_RX": "4", /*GPIO28*/
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"SCI_TX": "3" /*GPIO29*/
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}
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},
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"SPI": {
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"displayName": "SPIA BP",
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"description": "SPIA BoosterPack (BP) location on Site 1",
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"longDescription": "Site 1 of this LaunchPad features standard locations for SPI_CLK, SPI_STE, SPI_SIMO, and SPI_SOMI. Add this component to make use of the standard SPI BoosterPack (BP) signal locations.",
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"definition" : "/boards/components/standard_spi.json",
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"connections" : {
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"SPI_CLK": "75", /*GPIO9*/
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"SPI_STE": "37", /*GPIO11*/
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"SPI_SIMO": "58", /*GPIO8*/
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"SPI_SOMI": "76" /*GPIO10*/
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}
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},
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"I2C": {
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"displayName": "I2CA BP",
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"description": "I2CA BoosterPack (BP) location on Site 1",
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"longDescription": "Site 1 of this LaunchPad features standard locations for I2C_SCL and I2C_SDA. Add this component to make use of the standard I2C BoosterPack (BP) signal locations. \n\nNote: These signals are NOT connected to the LaunchPad connector by default. They require additional resistor soldering to complete the connection.",
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"definition" : "/boards/components/standard_i2c.json",
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"connections" : {
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"I2C_SCL": "50", /*GPIO18*/
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"I2C_SDA": "51" /*GPIO19*/
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}
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},
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"PWM_LOC1": {
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"displayName": "EPWM1 BP",
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"description": "EPWM1 BoosterPack (BP) location on Site 1",
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"longDescription": "Site 1 of this LaunchPad features standard locations for EPWM_A and EPWM_B. Add this component to make use of the standard EPWM BoosterPack (BP) signal locations.",
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"definition" : "/boards/components/standard_epwm.json",
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"connections" : {
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"EPWM_A": "1", /*GPIO30*/
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"EPWM_B": "62" /*GPIO1*/
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}
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},
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"PWM_LOC2": {
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"displayName": "EPWM2 BP",
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"description": "EPWM2 BoosterPack (BP) location on Site 1",
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"longDescription": "Site 1 of this LaunchPad features standard locations for EPWM_A and EPWM_B. Add this component to make use of the standard EPWM BoosterPack (BP) signal locations.",
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"definition" : "/boards/components/standard_epwm.json",
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"connections" : {
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"EPWM_A": "61", /*GPIO2*/
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"EPWM_B": "60" /*GPIO3*/
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}
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},
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"PWM_LOC3": {
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"displayName": "EPWM3 BP",
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"description": "EPWM3 BoosterPack (BP) location on Site 1",
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"longDescription": "Site 1 of this LaunchPad features standard locations for EPWM_A and EPWM_B. Add this component to make use of the standard EPWM BoosterPack (BP) signal locations.",
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"definition" : "/boards/components/standard_epwm.json",
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"connections" : {
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"EPWM_A": "63", /*GPIO0*/
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"EPWM_B": "78" /*GPIO15*/
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}
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}
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}
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},
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"BP_SITE_2": {
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"displayName": "Site 2 Standard BP",
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"description": "Standard BoosterPack (BP) module locations on Site 2 of LaunchPad",
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"longDescription": "All TI LaunchPads follow standard BoosterPack (BP) locations to ensure compatibility with BoosterPack peripherals. Site 2 on this LaunchPad features standard locations for three EPWM signals, CAN, SCI, and SPI.",
|
||
|
|
"subComponents": {
|
||
|
|
"SCI": {
|
||
|
|
"displayName": "SCIB BP",
|
||
|
|
"description": "SCIB BoosterPack (BP) location on Site 2",
|
||
|
|
"longDescription": "Site 2 of this LaunchPad features standard locations for SCI_RX and SCI_TX. Add this component to make use of the standard SCI BoosterPack (BP) signal locations.\n\n Note: Ensure that the on-board SCI switch is in the correct configuration to route SCIB to the BoosterPack headers.",
|
||
|
|
"definition" : "/boards/components/standard_sci.json",
|
||
|
|
"connections" : {
|
||
|
|
"SCI_RX": "65", /*GPIO23*/
|
||
|
|
"SCI_TX": "64" /*GPIO40*/
|
||
|
|
}
|
||
|
|
},
|
||
|
|
"SPI": {
|
||
|
|
"displayName": "SPIA BP",
|
||
|
|
"description": "SPIA BoosterPack (BP) location on Site 2",
|
||
|
|
"longDescription": "Site 2 of this LaunchPad features standard locations for SPI_CLK, SPI_STE, SPI_SIMO, and SPI_SOMI. Add this component to make use of the standard SPI BoosterPack (BP) signal locations. \n\nNote: These signals are NOT connected to the LaunchPad connector by default. They require additional resistor soldering to complete the connection.",
|
||
|
|
"definition" : "/boards/components/standard_spi.json",
|
||
|
|
"connections" : {
|
||
|
|
"SPI_CLK": "75", /*GPIO9*/
|
||
|
|
"SPI_STE": "46", /*GPIO37*/
|
||
|
|
"SPI_SIMO": "58", /*GPIO8*/
|
||
|
|
"SPI_SOMI": "76" /*GPIO10*/
|
||
|
|
}
|
||
|
|
},
|
||
|
|
"CAN": {
|
||
|
|
"displayName": "CANA BP",
|
||
|
|
"description": "CANA BoosterPack (BP) location on Site 2",
|
||
|
|
"longDescription": "Site 2 of this LaunchPad features standard locations for CAN_RX and CAN_TX. Add this component to make use of the standard CAN BoosterPack (BP) signal locations. \n\nNote: These signals pairs also have MCAN functionality muxed to them.",
|
||
|
|
"definition" : "/boards/components/standard_can.json",
|
||
|
|
"connections" : {
|
||
|
|
"CAN_TX": "59", /*GPIO4*/
|
||
|
|
"CAN_RX": "74" /*GPIO5*/
|
||
|
|
}
|
||
|
|
},
|
||
|
|
"PWM_LOC1": {
|
||
|
|
"displayName": "EPWM7 BP",
|
||
|
|
"description": "EPWM7 BoosterPack (BP) location on Site 2",
|
||
|
|
"longDescription": "Site 2 of this LaunchPad features standard locations for EPWM_A and EPWM_B. Add this component to make use of the standard EPWM BoosterPack (BP) signal locations.",
|
||
|
|
"definition" : "/boards/components/standard_epwm.json",
|
||
|
|
"connections" : {
|
||
|
|
"EPWM_A": "36", /*GPIO12*/
|
||
|
|
"EPWM_B": "35" /*GPIO13*/
|
||
|
|
}
|
||
|
|
},
|
||
|
|
"PWM_LOC2": {
|
||
|
|
"displayName": "EPWM4 BP",
|
||
|
|
"description": "EPWM4 BoosterPack (BP) location on Site 2",
|
||
|
|
"longDescription": "Site 2 of this LaunchPad features standard locations for EPWM_A and EPWM_B. Add this component to make use of the standard EPWM BoosterPack (BP) signal locations.",
|
||
|
|
"definition" : "/boards/components/standard_epwm.json",
|
||
|
|
"connections" : {
|
||
|
|
"EPWM_A": "80", /*GPIO6*/
|
||
|
|
"EPWM_B": "68" /*GPIO7*/
|
||
|
|
}
|
||
|
|
},
|
||
|
|
"PWM_LOC3": {
|
||
|
|
"displayName": "EPWM5 BP",
|
||
|
|
"description": "EPWM5 BoosterPack (BP) location on Site 2",
|
||
|
|
"longDescription": "Site 2 of this LaunchPad features standard locations for EPWM_A and EPWM_B. Add this component to make use of the standard EPWM BoosterPack (BP) signal locations.",
|
||
|
|
"definition" : "/boards/components/standard_epwm.json",
|
||
|
|
"connections" : {
|
||
|
|
"EPWM_A": "39", /*GPIO16*/
|
||
|
|
"EPWM_B": "40" /*GPIO17*/
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
},
|
||
|
|
"XDS_UART": {
|
||
|
|
"displayName": "XDS UART",
|
||
|
|
"description": "Route SCI UART connection to onboard XDS110 probe",
|
||
|
|
"longDescription": "On the LaunchPad, SCI signals can be routed from the TMS320F2800157 device to the debug module to allow for UART communication to and from the device. \n\nAdd this component to route SCI signals to the XDS110 debug probe. \n\n Note: Connection to the debug probe is dependent on the configuration of the on-board SCI Switch. Verify the switch placement to ensure the correct signals are routed to the XDS110 device.",
|
||
|
|
"subComponents": {
|
||
|
|
"XDS_SCI_INST1": {
|
||
|
|
"displayName": "SCIA XDS",
|
||
|
|
"description": "Route SCIA (GPIO28/29) signals",
|
||
|
|
"definition" : "/boards/components/sci_switch.json",
|
||
|
|
"longDescription": "Route GPIO28/29 SCIA signals to the XDS110 debug probe. \n\n Note: Ensure that the on-board SCI switch is in the correct configuration to route SCIA to the XDS110 probe.",
|
||
|
|
"connections" : {
|
||
|
|
"SCIRX": "4", /* GPIO28 */
|
||
|
|
"SCITX": "3" /* GPIO29 */
|
||
|
|
}
|
||
|
|
|
||
|
|
},
|
||
|
|
"XDS_SCI_INST2": {
|
||
|
|
"displayName": "SCIB XDS",
|
||
|
|
"description": "Route SCIB (GPIO23/40) signals",
|
||
|
|
"definition" : "boards/components/sci_switch.json",
|
||
|
|
"longDescription": "Route GPIO23/40 SCIB signals to the XDS110 debug probe. \n\n Note: Ensure that the on-board SCI switch is in the correct configuration to route SCIB to the XDS110 probe.",
|
||
|
|
"connections" : {
|
||
|
|
"SCIRX": "65", /* GPIO23 */
|
||
|
|
"SCITX": "64" /* GPIO40 */
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
},
|
||
|
|
"EQEP1_HEADER": {
|
||
|
|
"displayName": "EQEP1 Header",
|
||
|
|
"description": "Dedicated EQEP1 header on LaunchPad",
|
||
|
|
"longDescription": "This LaunchPad features a dedicated 5-pin EQEP1 connector for use with external BoosterPacks. Add this component to make use of the dedicated EQEP_A, EQEP_B, and EQEP_I signals. \n\nNote: Ensure the QEP Select Switch is configured to the proper position to make use of the EQEP1 header.",
|
||
|
|
"definition": "/boards/components/eqep.json",
|
||
|
|
"connections" : {
|
||
|
|
"EQEPA": "33", /* GPIO43 */
|
||
|
|
"EQEPB": "34", /* GPIO21 */
|
||
|
|
"EQEPI": "54" /* GPIO20 */
|
||
|
|
}
|
||
|
|
},
|
||
|
|
"EQEP2_HEADER": {
|
||
|
|
"displayName": "EQEP2 Header",
|
||
|
|
"description": "Dedicated EQEP2 header on LaunchPad",
|
||
|
|
"longDescription": "This LaunchPad features a dedicated 5-pin EQEP2 connector for use with external BoosterPacks. Add this component to make use of the dedicated EQEP_A, EQEP_B, and EQEP_I signals. \n\nNote: Ensure the QEP Select Switch is configured to the proper position to make use of the EQEP2 header.",
|
||
|
|
"definition": "/boards/components/eqep.json",
|
||
|
|
"connections" : {
|
||
|
|
"EQEPA": "79", /* GPIO26 */
|
||
|
|
"EQEPB": "38", /* GPIO33 */
|
||
|
|
"EQEPI": "43" /* GPIO14 */
|
||
|
|
}
|
||
|
|
},
|
||
|
|
"SCI_SWITCH": {
|
||
|
|
"displayName": "SCI Switches",
|
||
|
|
"description": "SCI Switches (S2)",
|
||
|
|
"longDescription": "This LaunchPad allows for one of two sets of pins to be used for the SCIA UART routed to the virtual COM port of the XDS110. \n\nBy default, GPIO28 (SCIA_RX) and GPIO29 (SCIA_TX) are routed to the virtual COM port and not available on the BoosterPack connector. Alternately, GPIO23 (SCIB_RX) and GPIO40 (SCIB_TX) can be routed to the virtual COM port. \n\nWhen UART functionality is not needed at the virtual COM port, the GPIOs can be routed to the BoosterPack connectors for BoosterPack standard functions. \n\nThe routing destination of these signal pairs are selected using the on-board switch S2. \n\n SEL1 (Left) | SEL2 (Right) | GPIO28/29 | GPIO23/40 \n -|-|-|- \n 0 (down) | 0 (down) | XDS110 COM Port | BP Headers \n 0 (down) | 1 (up) | XDS110 COM Port | No Connect \n 1 (up) | 0 (down) | BP Headers | BP Headers \n 1 (up) | 1 (up) | BP Headers | XDS110 COM Port",
|
||
|
|
},
|
||
|
|
"BOOT_SWITCH": {
|
||
|
|
"displayName": "Boot Switches",
|
||
|
|
"description": "Boot Switches (S3)",
|
||
|
|
"longDescription": "The F2800157 boot ROM contains bootloading software that executes every time the device is powered on or reset. Two pins, GPIO24 and GPIO32, are wired to the Boot Select switch (S3). By default, both pins are set HIGH (1) so the device will boot from Flash. \n\n GPIO24 (Left) | GPIO32 (Right) | Boot Mode \n -|-|- \n 0 (down) | 0 (down) | Boot from Parallel GPIO \n 0 (down) | 1 (up) | Boot from SCI/Wait boot \n 1 (up) | 0 (down) | Boot from CAN \n 1 (up) | 1 (up) | Boot from Flash (default)",
|
||
|
|
"subComponents": {
|
||
|
|
"SWITCH1": {
|
||
|
|
"displayName": "SW1",
|
||
|
|
"description": "SW1",
|
||
|
|
"definition" : "/boards/components/switch.json",
|
||
|
|
"longDescription": "Boot Switch",
|
||
|
|
"connections" : {
|
||
|
|
"INPUT": "41" /* GPIO24 */
|
||
|
|
}
|
||
|
|
|
||
|
|
},
|
||
|
|
"SWITCH2": {
|
||
|
|
"displayName": "SW2",
|
||
|
|
"description": "SW2",
|
||
|
|
"definition" : "/boards/components/switch.json",
|
||
|
|
"longDescription": "Boot Switch",
|
||
|
|
"connections" : {
|
||
|
|
"INPUT": "49" /* GPIO32 */
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
},
|
||
|
|
"CAN_SWITCH": {
|
||
|
|
"displayName": "CAN Route Switch",
|
||
|
|
"description": "CAN Route Switch (S4)",
|
||
|
|
"longDescription": "The LaunchPad can be connected to a CAN bus through J14. GPIO4 and GPIO5 are routed to the on-board TI TCAN332DR 3.3V CAN Transceiver, U8. \n\nBy setting S4 to DOWN (on), GPIO4 and GPIO5 are routed to the transceiver. If S4 is set to UP (off), the GPIOs are routed to the BoosterPack connectors (default case). \n\n CAN ROUTE | GPIO4/5 \n -|- \n BP (up) | BP Headers \n XCVR (down) | Transciever",
|
||
|
|
},
|
||
|
|
"QEP_SWITCH": {
|
||
|
|
"displayName": "QEP Select Switches",
|
||
|
|
"description": "QEP Select Switches (S5)",
|
||
|
|
"longDescription": "The LaunchPad has the ability to connect to two independent linear or rotary encoders through the F280015x on-chip eQEP interfaces: Header J12 is connected to eQEP1 and header J13 is connected to eQEP2. By default, this connection is not active and the GPIOs are routed to the BoosterPack connectors. \n\nThe 5 V eQEP input signals from the J12 and J13 connectors are stepped down through a TI SN74LVC8T245 Level Translator (U6) to 3.3 V. The signals are then routed through TI SN74LV4053A Triple 2-Channel Analog Multiplexer/ Demultiplexer ICs (U5/U7). \n\nSwitch S5 controls the select inputs of the ICs to configure the eQEP signal destinations to be either the J12/J13 connectors or BoosterPack headers. \n\n QEP1 SEL (LEFT) | QEP2 SEL (RIGHT) | QEP1 Signals (GPIO20/21/43) | QEP2 Signals (GPIO14/33/26) \n -|-|-|- \n 0 (down) | 0 (down) | J12 | J13 \n 0 (down) | 1 (up) | J12 | BP Headers \n 1 (up) | 0 (down) | BP Headers | J13 \n 1 (up) | 1 (up) | BP Headers | BP Headers",
|
||
|
|
},
|
||
|
|
"S2": {
|
||
|
|
"link": "BOOT_SWITCH"
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
}
|